Renesas RL78/G1P Hardware User Manual page 655

RL78/G1P
Figure 19-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
Supply voltage (V )
DD
V
LVDH
V
LVDL
Lower limit of operation voltage
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
LVIMK flag
(set by software)
Operation status
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
LVILV flag
LVIRF flag
LVD reset signal
POR reset signal
Internal reset signal
INTLVI
LVIIF flag
(Notes and Remark are listed on the next page.)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2)
If a reset is not generated after releasing the mask,
determine that a condition of V becomes V
DD
clear LVIMD bit to 0, and the MCU shift to normal operation.
Note 1
H
Cleared by
Normal
software
operation
Normal
Save
RESET
operation
processing
Cleared by
software
CHAPTER 19 VOLTAGE DETECTOR
V ,
DD LVDH
Cleared by software
Wait for stabilization by software (400 μs or 5 clocks of f
Normal
RESET
operation
Save
processing
Cleared by
software
Note 2
Time
RESET
Cleared
Note 3
Cleared
Note 3
)
IL
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