Based Indexed Addressing - Renesas RL78/G1P Hardware User Manual

RL78/G1P

3.4.8 Based indexed addressing

[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier

[HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)

ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
[HL +B],
<1> <2>
Instruction code
OP-code
A pair of registers <1> specifies the address where the target
array of data starts in the 64 KB area from F0000H to
FFFFFH.
Either register <2> specifies an offset within the array to
the target location in memory
ES: [HL +B], ES: [HL +C]
<1> <2> <3>
Instruction code
OP-code
byte
<3>
The ES register <1> specifies a 64 KB area within the overall
1 MB space as the four higher-order bits, X, of the address range.
A pair of registers <2> specifies the address where the target
array of data starts in the 64 KB area specified in the ES
register <1>.
Either register <3> specifies an offset within the array to the
target location in memory.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 3-30. Example of [HL+B], [HL+C]
[HL+C]
<1> <2>
r(B/C)
<1>
rp(HL)
Figure 3-31. Example of ES:[HL+B], ES:[HL+C]
<1> <2> <3>
<3>
r(B/C)
<2>
<2>
rp(HL)
<1>
<1>
ES
CHAPTER 3 CPU ARCHITECTURE
Description
Target memory
<2>
Offset
Address of
Other data in
an array
Memory
<3> Target memory
Offset
Address of
Other data in
the array
X0000H
Specifies a
64 KB area
FFFFFH
Target
array
of data
the array
F0000H
XFFFFH
Target
array
of data
the array
X0000H
Memory
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