Renesas RL78/G1P Hardware User Manual page 569

RL78/G1P
13.2 Configuration of DMA Controller
The DMA controller includes the following hardware.
Item
Address registers
Count register
Control registers
13.2.1 DMA SFR address register n (DSAn)
This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA channel n.
Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH.
This register is not automatically incremented but fixed to a specific value.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DSAn register can be read or written in 8-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 00H.
Address: FFFB0H (DSA0), FFFB1H (DSA1) After reset: 00H
7
DSAn
Remark n: DMA channel number (n = 0, 1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 13-1. Configuration of DMA Controller
 DMA SFR address registers 0, 1 (DSA0, DSA1)
 DMA RAM address registers 0, 1 (DRA0, DRA1)
 DMA byte count registers 0, 1 (DBC0, DBC1)
 DMA mode control registers 0, 1 (DMC0, DMC1)
 DMA operation control register 0, 1 (DRC0, DRC1)
Figure 13-1. Format of DMA SFR Address Register n (DSAn)
6 5 4 3 2
CHAPTER 13 DMA CONTROLLER
Configuration
R/W
1 0
550