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Renesas RL78/G1H User Manual

16-bit single-chip microcontrollers

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RL78/G1H

16

16-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev. 1.20

Dec 2016

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Summary of Contents for Renesas RL78/G1H

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
Page 4 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The RL78/G1H manual is separated into two parts: this manual and the software edition (common to the RL78 family). RL78/G1H RL78 Family User’s Manual...
Page 5 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. RL78/G1H User’s Manual Hardware This manual RL78 Family User’s Manual Software R01US0015E Documents Related to Flash Memory Programming (User’s Manual) Document Name Document No.
Page 6 All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
Page 7: Table Of Contents
CONTENTS OUTLINE ............................1 Features ........................... 1 Ordering Information ......................... 4 Pin Configuration (Top View) ....................6 Pin Identification ........................7 Block Diagram .......................... 8 Outline of Functions ........................9 CONNECTION BETWEEN MCU AND RF TRANSCEIVER ............11 Connection Pins of MCU and RF Transceiver ................. 11 Communication Interface Between MCU and RF Transceiver ..........
Page 8 5.2.6 Port 6 ..........................70 5.2.7 Port 7 ..........................70 5.2.8 Port 8 ..........................70 5.2.9 Port 10 ..........................71 5.2.10 Port 12 ..........................71 5.2.11 Port 13 ..........................71 5.2.12 Port 14 ..........................72 5.2.13 Port 15 ..........................72 5.2.14 GPIO port ...........................
Page 9 Controlling Clock ........................124 6.6.1 Example of setting high-speed on-chip oscillator ............. 124 6.6.2 Example of setting X1 oscillation clock ................126 6.6.3 Example of setting XT1 oscillation clock ................128 6.6.4 CPU clock status transition diagram ................. 129 6.6.5 Condition before changing CPU clock and processing after changing CPU clock ...
Page 10 Independent Channel Operation Function of Timer Array Unit ..........194 7.8.1 Operation as interval timer/square wave output ............... 194 7.8.2 Operation as external event counter ................199 7.8.3 Operation as input pulse interval measurement ............... 203 7.8.4 Operation as input signal high-/low-level width measurement ......... 207 7.8.5 Operation as delay counter ....................
Page 11 9.3.13 Alarm minute register (ALARMWM) ................. 251 9.3.14 Alarm hour register (ALARMWH) ..................251 9.3.15 Alarm week register (ALARMWW) ................... 251 Real-time Clock Operation ....................253 9.4.1 Starting operation of real-time clock ................. 253 9.4.2 Shifting to HALT/STOP mode after starting operation ............254 9.4.3 Reading/writing real-time clock ..................
Page 12 13.3.3 A/D converter mode register 1 (ADM1) ................295 13.3.4 A/D converter mode register 2 (ADM2) ................296 13.3.5 10-bit A/D conversion result register (ADCR) ..............298 13.3.6 8-bit A/D conversion result register (ADCRH) ..............298 13.3.7 Analog input channel specification register (ADS) ............299 13.3.8 Conversion result comparison upper limit setting register (ADUL) ........
Page 13 14.4 Operation Stop Mode ......................352 14.4.1 Stopping the operation by units ..................352 14.4.2 Stopping the operation by channels ................. 353 14.5 Operation of 3-Wire Serial I/O (CSIp) Communication ............354 14.5.1 Master transmission ......................356 14.5.2 Master reception ....................... 364 14.5.3 Master transmission/reception ..................
Page 14 15.5.15 Cautions ........................... 469 15.5.16 Communication operations ....................470 15.5.17 Timing of I C interrupt request (INTIICAn) occurrence ............. 478 15.6 Timing Charts ........................499 DATA TRANSFER CONTROLLER (DTC) .................. 514 16.1 Functions of DTC ........................514 16.2 Configuration of DTC ......................516 16.3 Registers Controlling DTC ....................
Page 15 18.3 Configuration of RF Transceiver ................... 548 18.3.1 Digital block ........................548 18.3.2 Analog block ........................549 18.3.3 Oscillator block ......................... 550 18.3.4 Power supply block ......................550 18.4 Baseband Function ....................... 551 18.4.1 Configuration ........................551 18.4.2 Frame configuration ......................552 18.4.3 Baseband Interrupt ......................
Page 16 20.2 Registers controlling standby function .................. 732 20.3 Standby Function Operation ....................733 20.3.1 HALT mode ........................733 20.3.2 STOP mode ........................738 20.3.3 SNOOZE mode ........................ 743 RESET FUNCTION ........................746 21.1 Timing of Reset Operation ....................748 21.2 Register for Confirming Reset Source ..................
Page 17 26.1.2 On-chip debug option byte (000C3H/ 010C3H) ..............798 26.2 Format of User Option Byte ....................799 26.3 Format of On-chip Debug Option Byte ................. 805 FLASH MEMORY ........................806 27.1 Serial Programming Using Flash Memory Programmer ............807 27.1.1 Programming Environment ....................
Page 18 ELECTRICAL SPECIFICATIONS ....................856 31.1 Absolute Maximum Ratings ....................857 31.2 Oscillator Characteristics ...................... 859 31.2.1 X1, XT1 characteristics ..................... 859 31.2.2 On-chip oscillator characteristics ..................859 31.3 DC Characteristics ........................ 860 31.3.1 Pin characteristics ......................860 31.3.2 Supply current characteristics ..................865 31.4 AC Characteristics ........................
Page 19: Outline
Dec 22, 2016 CHAPTER 1 OUTLINE RL78/G1H is a microcontroller equipped with the low-power-consumption RF transceiver compatible with the SubGHz- band wireless communication. The wireless communication in the SubGHz band is best for the smart meter communication part, HEMS controller, wireless sensor network, etc.
Page 20 RL78/G1H CHAPTER 1 OUTLINE Data flash memory • Data flash memory: 8 KB • Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. • Number of rewrites: 1,000,000 times (TYP.) • Voltage of rewrites: V = 1.8 to 3.6 V...
Page 21 RL78/G1H CHAPTER 1 OUTLINE Cipher • AES cipher processing (128-bit key length) • Random number generator (true random number, complies with AIS31 standard) Others • On-chip BCD (binary-coded decimal) correction circuit ROM, RAM capacities Flash ROM Data flash RL78/G1H 256 KB...
Page 22: Ordering Information
RL78/G1H CHAPTER 1 OUTLINE Ordering Information Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1H Part No. R 5 F 1 1 F L L A x x x N A # 2 0 Packaging specification #20: Tray...
Page 23 R5F11FLLDNA#40 Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1H . Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website.
Page 24: Pin Configuration (Top View)
RL78/G1H CHAPTER 1 OUTLINE Pin Configuration (Top View) • 64-pin plastic HVQFN (9 × 9) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 REGIN GPIO1/ANTSELOUT0 VSSDDC GPIO0/CLKOUT DDCOUT INTOUT VCCDDC STANDBY P100...
Page 25: Pin Identification
RL78/G1H CHAPTER 1 OUTLINE Pin Identification <MCU unit> ANI0 to ANI2, ANI13: Analog Input P130, P137: Port 13 ANI14, ANI19: Analog Input P140 to P144: Port 14 Analog Reference P155, P156: Port 15 REFM Voltage Minus PCLBUZ0, PCLBUZ1: Programmable Clock Output/...
Page 26: Block Diagram
RL78/G1H CHAPTER 1 OUTLINE Block Diagram MCU part POR/LVD TIMER ARRAY TIMER ARRAY CONTROL UNIT0 (4ch) UNIT1 (4ch) POWER ON RESET/ VOLTAGE DETECTOR RESET TI03/TO03 CONTROL ANI0 to ANI2 ON-CHIP DEBUG TOOL0 BUZZER OUTPUT ANI13, ANI14 PCLBUZ0 A/D CONVERTER PCLBUZ1...
Page 27: Outline Of Functions
RL78/G1H CHAPTER 1 OUTLINE Outline of Functions (1/2) Item R5F11FLJ R5F11FLK R5F11FLL Code flash memory (KB) 256 KB 384 KB 512 KB Data flash memory (KB) 8 KB 8 KB 8 KB RAM (KB) 24 KB 32 KB Note 1...
Page 28 RL78/G1H CHAPTER 1 OUTLINE (2/2) Item R5F11FLJ R5F11FLK R5F11FLL Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: f = 20 MHz operation) MAIN • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: f = 32.768 kHz operation)
Page 29: Connection Between Mcu And Rf Transceiver
CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Connection Pins of MCU and RF Transceiver Table 2 - 1 lists the pins connected inside the RL78/G1H. Table 2 - 2 lists the pins which need to be connected on the board by the user.
Page 30: Communication Interface Between Mcu And Rf Transceiver
RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Communication Interface Between MCU and RF Transceiver 3-wire serial I/O (CSI) is used for the SPI interface for internal communication between the MCU and RF unit. For data transfer between the MCU and RF unit, a transfer clock is output from the MCU to the RF unit and data is transmitted and received.
Page 31: Initial Settings Of Unused Internal Pins Of Mcu
RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Initial Settings of Unused Internal Pins of MCU After reset release, the following internal pins of the MCU need to be set to output mode (set the port registers and port mode registers to 0) by software.
Page 32: Base Operation Clock Of Rf Unit
RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Base Operation Clock of RF Unit RF unit operation requires a 48 MHz clock. Table 2 - 4 shows clock resonator connection and Figure 2 - 1 shows the clock configuration.
Page 33: Power Configuration
DC-DC converter is output to the DDCOUT pin. The power is smoothed by an inductor and capacitor to step down the voltage, and then supplied to the REGIN. Figure 2 - 2 shows the power configuration of the RL78/G1H. Figure 2 - 2 Power Configuration 1.8 to 3.6 V...
Page 34: Peripheral Circuits'connection Diagram
RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Peripheral Circuits’Connection Diagram Figure 2 - 3 RL78/G1H (64-pin) Peripheral Circuits’Connection Diagram (without ANTSW) VCC(3V) XTAL(48MHz) 49.REGIN 32.GPIO1 50.VSSDDC 31.GPIO0 51.DDCOUT 30.INTOUT 52.VCCDDC 29.P82 53.STANDBY 28.P81 54.P100 27.P80 55.P156 26.P70 56.P155 25.P71...
Page 35 RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Figure 2 - 4 RL78/G1H (64-pin) Peripheral Circuits’Connection Diagram (with ANTSW) VCC(3V) RFSW XTAL(48MHz) 49.REGIN 32.GPIO1 50.VSSDDC 31.GPIO0 51.DDCOUT 30.INTOUT 52.VCCDDC 29.P82 28.P81 53.STANDBY 27.P80 54.P100 26.P70 55.P156 64HVQFN 25.P71 56.P155 57.P22...
Page 36 RL78/G1H CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Figure 2 - 5 RL78/G1H (64-pin) Peripheral Circuit Connection Diagram (Using TCXO) VCC(3V) TCXO 49.REGIN 32.GPIO1 50.VSSDDC 31.GPIO0 51.DDCOUT 30.INTOUT 52.VCCDDC 29.P82 53.STANDBY 28.P81 54.P100 27.P80 55.P156 26.P70 56.P155 25.P71 57.P22 24.P72...
Page 37: Pin Functions
RL78/G1H CHAPTER 3 PIN FUNCTIONS CHAPTER 3 PIN FUNCTIONS Port Functions Pin I/O buffer power supplies depend on the pin. The relationship between these power supplies and the pins is shown below. Table 3 - 1 Pin I/O Buffer Power Supplies...
Page 38 RL78/G1H CHAPTER 3 PIN FUNCTIONS Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions. (1/2) Function After Reset Pin Type Alternate Function Function Name Release Prohibit SO10/TxD1 Port 0. Note 1 7-3-4 Note 2 3-bit I/O port.
Page 39 RL78/G1H CHAPTER 3 PIN FUNCTIONS (2/2) Function After Reset Pin Type Alternate Function Function Name Release 8-1-4 Input port — Port 8. 3-bit I/O port. — Input/output can be specified in 1-bit units. 7-1-4 — Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Page 40: Functions Other Than Port Pins
RL78/G1H CHAPTER 3 PIN FUNCTIONS Functions other than port pins Function Name Function ANI0 to ANI2, ANI13, ANI14, A/D converter analog input (see Figure 13 - 30 Analog Input Pin Connection ) Input ANI19 External interrupt request input INTP0, INTP3...
Page 41: Connection Of Unused Pins
RL78/G1H CHAPTER 3 PIN FUNCTIONS Connection of Unused Pins Table 3 - 3 shows the Connection of Unused Pins. <R> Table 3 - 3 Connection of Unused Pins Pin Name Recommended Connection of Unused Pins P02 to P04 Input: Independently connect to V or V via a resistor.
Page 42: Pin Block Diagrams
RL78/G1H CHAPTER 3 PIN FUNCTIONS Pin Block Diagrams For the pin types listed in 3.1 Port Functions, pin block diagrams are shown in Figures 3 - 1 to 3 - 13. Figure 3 - 1 Pin Block Diagram of Pin Type 1-1-1...
Page 43 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 4 Pin Block Diagram of Pin Type 2-2-1 Clock generator OSCSEL/ OSCSELS Alternate function P122/X2/EXCLK/Alternate function P124/XT2/EXCLKS/Alternate function EXCLK, OSCSEL/ EXCLKS, OSCSELS N-ch P-ch Alternate function P121/X1/Alternate function P123/XT1/Alternate function Remark Refer to 3.1 Port Functions for alternate functions.
Page 44 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 5 Pin Block Diagram of Pin Type 4-3-3 ADPC ADPC 0: Analog input 1: Digital I/O ADPC3 to ADPC0 PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) PMS register P-ch...
Page 45 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 6 Pin Block Diagram of Pin Type 7-1-3 Alternate function PU register P-ch (PUmn) Schmitt2 PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remark 1.
Page 46 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 7 Pin Block Diagram of Pin Type 7-1-4 Alternate function PU register P-ch (PUmn) Schmitt2 PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) POM register (POMmn) Alternate function...
Page 47 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 8 Pin Block Diagram of Pin Type 7-3-3 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function Schmitt2 PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) Alternate function...
Page 48 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 9 Pin Block Diagram of Pin Type 7-3-4 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function Schmitt2 PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) POM register...
Page 49 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 10 Pin Block Diagram of Pin Type 8-1-3 PU register (PUmn) P-ch PIM register (PIMmn) Alternate function Schmitt2 CMOS PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) Alternate function...
Page 50 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 11 Pin Block Diagram of Pin Type 8-1-4 PU register (PUmn) P-ch PIM register (PIMmn) Alternate function Schmitt2 CMOS PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) POM register...
Page 51 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 12 Pin Block Diagram of Pin Type 8-3-4 PU register (PUmn) P-ch PIM register (PIMmn) PMC register (PMCmn) Alternate function PORT Schmitt2 CMOS PORT Output latch (Pmn) P-ch N-ch PMS register PM register...
Page 52 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 13 Pin Block Diagram of Pin Type 12-1-2 Alternate function PORT Schmitt1 PORT Output latch (Pmn) N-ch PMS register PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remark 1. Refer to 3.1 Port Functions for alternate functions.
Page 53 RL78/G1H CHAPTER 3 PIN FUNCTIONS Figure 3 - 14 Pin Block Diagram of STANDBY, MODE1, MODE2 STANDBY, MODE1, MODE2 Input Figure 3 - 15 Pin Block Diagram of Pin GPIO0 to GPIO4 Output enable GPIO0 to GPIO4 Data Input Input enable...
Page 54: Cpu Architecture
CHAPTER 4 CPU ARCHITECTURE CHAPTER 4 CPU ARCHITECTURE Memory Space Products in the RL78/G1H can access a 1 MB address space. Figures 4 - 1 to 4 - 3 show the memory maps. R01UH0575EJ0120 Rev. 1.20 Page 36 of 920...
Page 55 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Figure 4 - 1 Memory Map (R5F11FLJ) FFFFFH 3FFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 Program area 24 Kbytes F9F00H F9EFFH Mirror 27.75 Kbytes...
Page 56 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Figure 4 - 2 Memory Map (R5F11FLK) FFFFFH 5FFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H Notes 1, 2 FFEDFH Program area 32 Kbytes F7F00H F7EFFH Mirror 19.75 Kbytes...
Page 57 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Figure 4 - 3 Memory Map (R5F11FLL) FFFFFH 7FFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 Program area 48 Kbytes F3F00H F3EFFH Mirror 3.75 Kbytes...
Page 58 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Tables 4 - 1 to 4 - 4 Correspondence Between Address Values and Block Numbers in Flash Memory .
Page 59 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 2 Correspondence Between Address Values and Block Numbers in Flash Memory (2/4) Block Block Block Block Address Value Address Value Address Value Address Value Number Number Number Number 20000H to 203FFH 28000H to 283FFH...
Page 60 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 3 Correspondence Between Address Values and Block Numbers in Flash Memory (3/4) Block Block Block Block Address Value Address Value Address Value Address Value Number Number Number Number 40000H to 403FFH 100H...
Page 61 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 4 Correspondence Between Address Values and Block Numbers in Flash Memory (4/4) Block Block Block Block Address Value Address Value Address Value Address Value Number Number Number Number 60000H to 603FFH 180H...
Page 62: Internal Program Memory Space
RL78/G1H CHAPTER 4 CPU ARCHITECTURE 4.1.1 Internal program memory space The internal program memory space stores the program and table data. The internal program memory space is divided into the following areas. (1) Vector table area The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area.
Page 63: Mirror Area
RL78/G1H CHAPTER 4 CPU ARCHITECTURE 4.1.2 Mirror area The code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)).
Page 64: Internal Data Memory Space
RL78/G1H CHAPTER 4 CPU ARCHITECTURE 4.1.3 Internal data memory space The internal RAM can be used as a data area and a program area where instructions are fetched (it is prohibited to use the general-purpose register area for fetching instructions). Four general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM area.
Page 65: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G1H, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general- purpose registers are available for use.
Page 66: Processor Registers
RL78/G1H CHAPTER 4 CPU ARCHITECTURE Processor Registers The RL78/G1H products incorporate the following processor registers. 4.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 67 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Zero flag (Z) When the operation result is zero or equal, this flag is set (1). It is reset (0) in all other cases. Register bank select flags (RBS0, RBS1) These are 2-bit flags to select one of the four register banks.
Page 68 RL78/G1H CHAPTER 4 CPU ARCHITECTURE In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Caution 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack.
Page 69: General-Purpose Registers
RL78/G1H CHAPTER 4 CPU ARCHITECTURE 4.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Page 70: Es And Cs Registers
RL78/G1H CHAPTER 4 CPU ARCHITECTURE 4.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Page 71: Special Function Registers (Sfrs)
RL78/G1H CHAPTER 4 CPU ARCHITECTURE 4.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 72 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 5 Special Function Register (SFR) List (1/5) Manipulable Bit Range Special Function Register (SFR) Address Symbol After Reset Name 1-bit 8-bit 16-bit FFF00H Port register 0 √ √ — FFF01H Port register 1 √...
Page 73 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 6 Special Function Register (SFR) List (2/5) Manipulable Bit Range Special Function Register (SFR) Address Symbol After Reset Name 1-bit 8-bit 16-bit FFF28H Port mode register 8 √ √ — FFF2AH Port mode register 10 PM10 √...
Page 74 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 7 Special Function Register (SFR) List (3/5) Manipulable Bit Range Special Function Register (SFR) Address Symbol After Reset Name 1-bit 8-bit 16-bit FFF72H Timer data register 11 TDR11L TDR11 — √ √...
Page 75 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 8 Special Function Register (SFR) List (4/5) Manipulable Bit Range Special Function Register (SFR) Address Symbol After Reset Name 1-bit 8-bit 16-bit FFFA8H Reset control flag register RESF — √ — Note 1 Undefined √...
Page 76 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 9 Special Function Register (SFR) List (5/5) Manipulable Bit Range Address Special Function Register (SFR) Name Symbol After Reset 1-bit 8-bit 16-bit √ √ √ FFFE0H Interrupt request flag register 0L IF0L √...
Page 77: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
RL78/G1H CHAPTER 4 CPU ARCHITECTURE 4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2 SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
Page 78 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 10 Extended Special Function Register (2nd SFR) List (1/7) Manipulable Bit Range Extended Special Function Register Address Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit F0010H A/D converter mode register 2 ADM2 √...
Page 79 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 11 Extended Special Function Register (2nd SFR) List (2/7) Manipulable Bit Range Extended Special Function Register Address Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit √ √ F00F0H Peripheral enable register 0 PER0 —...
Page 80 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 12 Extended Special Function Register (2nd SFR) List (3/7) Manipulable Bit Range Extended Special Function Register Address Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit √ √ √ F0122H Serial channel start register 0...
Page 81 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 13 Extended Special Function Register (2nd SFR) List (4/7) Manipulable Bit Range Extended Special Function Register Address Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit √ F015CH Serial communication operation SCR12 —...
Page 82 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 14 Extended Special Function Register (2nd SFR) List (5/7) Manipulable Bit Range Extended Special Function Register Address Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit √ √ F01A6H Timer status register 03...
Page 83 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 15 Extended Special Function Register (2nd SFR) List (6/7) Manipulable Bit Range Extended Special Function Register Address Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit √ √ F01E6H Timer status register 13...
Page 84 RL78/G1H CHAPTER 4 CPU ARCHITECTURE Table 4 - 16 Extended Special Function Register (2nd SFR) List (7/7) Manipulable Bit Range Extended Special Function Register Address Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit √ F02FAH CRC data register CRCD —...
Page 85: Port Functions
CHAPTER 5 PORT FUNCTIONS Port Functions The RL78/G1H microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 3 PIN FUNCTIONS.
Page 86: Port Configuration
RL78/G1H CHAPTER 5 PORT FUNCTIONS Port Configuration Ports include the following hardware. Table 5 - 1 Port Configuration Item Configuration Control registers Port mode registers (PM0 to PM8, PM10 to PM12, PM14, PM15) Port registers (P0 to P8, P10 to P15)
Page 87: Port 0
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P02 to P04 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 88: Port 3
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30, P31 pins are used as input ports, use of on-chip pull-up resistors can be specified by pull-up resistor option register 3 (PU3).
Page 89: Port 10
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 10 Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (PM10). When the P100 to P102 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 10 (PU10).
Page 90: Port 12
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.2.12 Port 14 Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P144 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Page 91: Registers Controlling Port Function
RL78/G1H CHAPTER 5 PORT FUNCTIONS Registers Controlling Port Function Port functions are controlled by the following registers. • Port mode registers (PMxx) • Port registers (Pxx) • Pull-up resistor option registers (PUxx) • Port input mode registers (PIMxx) • Port output mode registers (POMxx) •...
Page 92 RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 4 PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits (1/2) Bit name Port PMxx PUxx PIMxx POMxx PMCxx register register register register register register Port 0 PM02 PU02 — POM02...
Page 93 RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 5 PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits (2/2) Bit name Port PMxx PUxx PIMxx POMxx PMCxx register register register register register register Port 14 PM140 P140 PU140 —...
Page 94: Port Mode Registers (Pmxx)
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
Page 95 RL78/G1H CHAPTER 5 PORT FUNCTIONS Note 1. Control bits for internal pins. After reset release, be sure to set to output mode by software (set 0 to port mode register). Note 2. Control bits for internal connecting pins. After reset release, be sure to set to output mode by software (set 0 to port mode register).
Page 96: Port Registers (Pxx)
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...
Page 97 RL78/G1H CHAPTER 5 PORT FUNCTIONS Figure 5 - 2 Format of Port register Symbol Address After reset FFF00H 00H (output latch) Note 3 Note 3 Note 3 Note 3 FFF01H 00H (output latch) Note 3 FFF02H 00H (output latch) Note 3...
Page 98: Pull-Up Resistor Option Registers (Puxx)
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
Page 99: Port Input Mode Registers (Pimxx)
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.3.4 Port input mode registers (PIMxx) These registers set the input buffer in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 100: Port Output Mode Registers (Pomxx)
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.3.5 Port output mode registers (POMxx) These registers set the output mode in 1-bit units. N-ch open-drain output (V tolerance) mode can be selected during serial communication with an external device of the different potential.
Page 101: Port Mode Control Registers (Pmcxx)
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.3.6 Port mode control registers (PMCxx) These registers set the P02, P03, P100, P120, and P147 digital I/O/analog input in 1-bit units. PMC0, PMC10, PMC12, and PMC14 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 102: A/D Port Configuration Register (Adpc)
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.3.7 A/D port configuration register (ADPC) This register is used to switch the P20/ANI0, P21/ANI1, P22/ANI2, ANI13/P155, and ANI14/P156 pins to digital I/O of port or analog function of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction.
Page 103: Port Function Operations
RL78/G1H CHAPTER 5 PORT FUNCTIONS Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 104: Handling Different Potential (1.8 V, 2.5 V, 3 V) By Using I/O Buffers
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.4.4 Handling different potential (1.8 V, 2.5 V, 3 V) by using I/O buffers It is possible to connect an external device operating on a different potential (1.8 V, 2.5 V, or 3 V) by switching I/O buffers with the port input mode register (PIMxx) and port output mode register (POMxx).
Page 105: Register Settings When Using Alternate Function
RL78/G1H CHAPTER 5 PORT FUNCTIONS Register Settings When Using Alternate Function 5.5.1 Basic concept when using alternate function In the beginning, for a pin also assigned to be used for analog function, use the ADPC register or port mode control register (PMCxx) to specify whether to use the pin for analog function or digital input/output.
Page 106: Register Settings For Alternate Function Whose Output Function Is Not Used
RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 6 Concept of Basic Settings Output Settings of Unused Alternate Function Output Function of Used Pin Output Function for Port Output Function for SAU Output Function for other than SAU Output function for port —...
Page 107: Register Setting Examples For Used Port And Alternate Functions
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.5.3 Register setting examples for used port and alternate functions Register setting examples for used port and alternate functions are shown in Tables 5 - 7 to 5 - 12. The registers used to control the port functions should be set as shown in Tables 5 - 7 to 5 - 12. See the following remark for legends used in Tables 5 - 7 to 5 - 12.
Page 108 RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 8 Setting Examples of Registers When Using P20 to P22 Pin Function Used Function Pin Name ADPC ADM2 PMxx Function Name Input ADPC = 01H × × Output ADPC = 01H ×...
Page 109 RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 9 Setting Examples of Registers When Using P30 to P120 Pin Function (1/2) Used Function Alternate Function Output POMxx PMCxx PMxx SAU Output Name Function Name Other than SAU Function Input ―...
Page 110 RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 9 Setting Examples of Registers When Using P30 to P120 Pin Function (2/2) Used Function Alternate Function Output POMxx PMCxx PMxx SAU Output Name Function Name Other than SAU Function Input ―...
Page 111 RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 11 Setting Examples of Registers When Using P130 to P144 Pin Function Used Function Alternate Function Output POMxx PMCxx PMxx SAU Output Name Function Name Other than SAU Function P130 P130 Output ―...
Page 112 RL78/G1H CHAPTER 5 PORT FUNCTIONS Table 5 - 12 Setting Examples of Registers When Using P155 and P156 Pin Function Used Function Pin Name ADPC PMxx Function Name P155 P155 Input ADPC = 01H to 0EH × Output ADPC = 01H to 0EH...
Page 113: Cautions When Using Port Function
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/G1H. <1> The Pn register is read in 8-bit units.
Page 114: Notes On Specifying The Pin Settings
RL78/G1H CHAPTER 5 PORT FUNCTIONS 5.6.2 Notes on specifying the pin settings For an output pin to which multiple functions are assigned, the output of the unused alternate functions must be set to its initial state so as to prevent conflicting outputs. For details about the alternate function output, see 5.5 Register Settings When Using Alternate Function.
Page 115: Clock Generator
RL78/G1H CHAPTER 6 CLOCK GENERATOR CHAPTER 6 CLOCK GENERATOR For details about the clock generator for the RF transceiver, see 2.4 Base Operation Clock of RF Unit. Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
Page 116 RL78/G1H CHAPTER 6 CLOCK GENERATOR (3) Low-speed on-chip oscillator (Low-speed OCO) This circuit oscillates a clock of f = 15 kHz (TYP.). The low-speed on-chip oscillator clock cannot be used as the CPU clock. Only the following peripheral hardware runs on the low-speed on-chip oscillator clock.
Page 117: Configuration Of Clock Generator
RL78/G1H CHAPTER 6 CLOCK GENERATOR Configuration of Clock Generator The clock generator includes the following hardware. Table 6 - 1 Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC)
Page 118 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 1 Block Diagram of Clock Generator (Remark is listed on the next page after next.) R01UH0575EJ0120 Rev. 1.20 Page 100 of 920 Dec 22, 2016...
Page 119: Registers Controlling Clock Generator
RL78/G1H CHAPTER 6 CLOCK GENERATOR Remark X1 clock oscillation frequency High-speed on-chip oscillator clock frequency External main system clock frequency High-speed system clock frequency Main system clock frequency MAIN XT1 clock oscillation frequency External subsystem clock frequency Subsystem clock frequency...
Page 120 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 2 Format of Clock operation mode control register (CMC) Address: FFFA0H After reset: 00H Symbol EXCLK OSCSEL EXCLKS OSCSELS AMPHS1 AMPHS0 AMPH High-speed system clock EXCLK OSCSEL X1/P121 pin X2/EXCLK/P122 pin pin operation mode...
Page 121 RL78/G1H CHAPTER 6 CLOCK GENERATOR Caution 7. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. • Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems.
Page 122: System Clock Control Register (Ckc)
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 123: Clock Operation Status Control Register (Csc)
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 124: Oscillation Stabilization Time Counter Status Register (Ostc)
RL78/G1H CHAPTER 6 CLOCK GENERATOR Table 6 - 2 Stopping Clock Method Condition Before Stopping Clock Clock Setting of CSC Register Flags (Invalidating External Clock Input) X1 clock CPU and peripheral hardware clocks operate with a clock MSTOP = 1 other than the high-speed system clock.
Page 125 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 5 Format of Oscillation stabilization time counter status register (OSTC) Address: FFFA2H After reset: 00H Symbol MOST MOST MOST MOST MOST MOST OSTC MOST8 MOST9 Oscillation stabilization time status MOST MOST MOST...
Page 126: Oscillation Stabilization Time Select Register (Osts)
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. When the X1 clock is made to oscillate by clearing the MSTOP bit to start the X1 oscillation circuit operating, actual operation is automatically delayed for the time set in the OSTS register.
Page 127 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 6 Format of Oscillation stabilization time select register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection OSTS2 OSTS1 OSTS0 = 10 MHz = 20 MHz 25.6 μ...
Page 128: Peripheral Enable Registers 0, 1 (Per0, Per1)
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.3.6 Peripheral enable registers 0, 1 (PER0, PER1) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
Page 129 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 8 Format of Peripheral enable register 0 (PER0) (2/3) Address: F00F0H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN...
Page 130 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 9 Format of Peripheral enable register 0 (PER0) (3/3) Address: F00F0H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN PER0...
Page 131 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 10 Format of Peripheral enable register 1 (PER1) Address: F007AH After reset: 00H Symbol <3> <0> PER1 DTCEN TRJ0EN DTCEN Control of DTC input clock supply Stops input clock supply. • DTC cannot run.
Page 132: Subsystem Clock Supply Mode Control Register (Osmc)
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.3.7 Subsystem clock supply mode control register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock and 12-bit interval timer, is stopped in STOP mode or HALT mode while subsystem clock is selected as CPU clock.
Page 133: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV).
Page 134: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input, and so on, the accuracy can be adjusted.
Page 135: System Clock Oscillator
RL78/G1H CHAPTER 6 CLOCK GENERATOR System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
Page 136 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 15 Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock 32.768 External clock EXCLKS Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6 - 14 and 6 - 15 to avoid an adverse effect from wiring capacitance.
Page 137 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 16 shows examples of incorrect resonator connection. Figure 6 - 16 Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross.
Page 138 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 17 Examples of Incorrect Resonator Connection (2/2) (f) Current flowing through ground line of oscillator (e) Wiring near high alternating current (potential at points A, B, and C fluctuates) High current (g) Signals are fetched...
Page 139: High-Speed On-Chip Oscillator
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.4.3 High-speed on-chip oscillator The frequency can be selected from among 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC).
Page 140: Clock Generator Operation
RL78/G1H CHAPTER 6 CLOCK GENERATOR Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 6 - 1). • Main system clock MAIN • High-speed system clock...
Page 141 RL78/G1H CHAPTER 6 CLOCK GENERATOR Figure 6 - 18 Clock Generator Operation When Power Supply Voltage Is Turned On 10 µs or more Lower limit of the operating voltage range Power supply voltage (V <1> Power-on-reset RESET pin Switched by software...
Page 142: Controlling Clock
RL78/G1H CHAPTER 6 CLOCK GENERATOR Controlling Clock 6.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on- chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 6, <R>...
Page 143 RL78/G1H CHAPTER 6 CLOCK GENERATOR [High-speed on-chip oscillator frequency select register (HOCODIV) setting] Address: F00A8H Symbol HOCODIV HOCODIV2 HOCODIV1 HOCODIV0 Selection of high-speed on-chip oscillator clock frequency HOCODIV2 HOCODIV1 HOCODIV0 FRQSEL3 = 0 FRQSEL3 = 1 = 24 MHz = 32 MHz...
Page 144: Example Of Setting X1 Oscillation Clock
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on- chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start...
Page 145 RL78/G1H CHAPTER 6 CLOCK GENERATOR Caution Change the main system clock (f ) by the CKC register within the operable voltage range of the MAIN flash operation mode set in the option byte (000C2H) before and after the clock change.
Page 146: Example Of Setting Xt1 Oscillation Clock
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on- chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start...
Page 147: Cpu Clock Status Transition Diagram
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.6.4 CPU clock status transition diagram Figure 6 - 19 shows the CPU clock status transition diagram of this product. Figure 6 - 19 CPU Clock Status Transition Diagram Power ON High-speed on-chip oscillator: Woken up...
Page 148 RL78/G1H CHAPTER 6 CLOCK GENERATOR Tables 6 - 3 to 6 - 7 show transition of the CPU clock and examples of setting the SFR registers. Table 6 - 3 CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Page 149 RL78/G1H CHAPTER 6 CLOCK GENERATOR Table 6 - 4 CPU Clock Transition and SFR Register Setting Examples (2/5) (4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register...
Page 150 RL78/G1H CHAPTER 6 CLOCK GENERATOR Table 6 - 5 CPU Clock Transition and SFR Register Setting Examples (3/5) (6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register...
Page 151 RL78/G1H CHAPTER 6 CLOCK GENERATOR Table 6 - 6 CPU Clock Transition and SFR Register Setting Examples (4/5) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register...
Page 152 RL78/G1H CHAPTER 6 CLOCK GENERATOR Table 6 - 7 CPU Clock Transition and SFR Register Setting Examples (5/5) (11) • STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B) • STOP mode (I) set while CPU is operating with high-speed system clock (C)
Page 153: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6 - 8 Changing CPU Clock (1/2)
Page 154 RL78/G1H CHAPTER 6 CLOCK GENERATOR Table 6 - 9 Changing CPU Clock (2/2) CPU Clock Condition Before Change Processing After Change Before Change After Change XT1 clock High-speed on-chip Oscillation of high-speed on-chip oscillator After checking that the CPU clock is...
Page 155: Time Required For Switchover Of Cpu Clock And Main System Clock
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.6.6 Time required for switchover of CPU clock and main system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the high-speed on-chip oscillator clock and the high-speed system clock).
Page 156: Conditions Before Clock Oscillation Is Stopped
RL78/G1H CHAPTER 6 CLOCK GENERATOR 6.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Check the condition before stopping clock before stopping the clock.
Page 157: Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT CHAPTER 7 TIMER ARRAY UNIT Timer array unit incorporates 8 channels of 16-bit timer (4 channels of 16-bit timer × 2 units) in total. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.
Page 158: Functions Of Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Functions of Timer Array Unit Timer array unit has the following functions. 7.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
Page 159: Simultaneous Channel Operation Function
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT (6) Delay counter Counting is started at the valid edge of the signal input to the timer input pin (TImn), and an interrupt is generated after any delay period. C om pare operation Tim er input...
Page 160: Configuration Of Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 7 - 1 Configuration of Timer Array Unit Item Configuration Timer/counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn)
Page 161 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 1 Entire Configuration of Timer Array Unit 0 Timer clock select register 0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Timer input select register 0 (TIS0)
Page 162 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 2 Internal Block Diagram of Channel 0 of Timer Array Unit 0 Timer input select register 0 (TIS0) TIS04 TIS02 TIS01 TIS00 Timer CK00 TCLK controller Mode CK01 selection Interrupt controller...
Page 163 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 4 Internal Block Diagram of Channel 2 of Timer Array Unit 0 Interrupt signal from master channel Timer CK00 TCLK controller CK01 Mode selection Interrupt controller INTTM02 (Timer interrupt) Timer counter register 02 (TCR02)
Page 164: Timer Count Register Mn (Tcrmn)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.2.1 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Page 165 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT The count value can be read by reading timer count register mn (TCRmn). The count value is set to FFFFH in the following cases. • When the reset signal is generated • When the TAUmEN bit of peripheral enable register 0 (PER0) is cleared •...
Page 166: Timer Data Register Mn (Tdrmn)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
Page 167: Registers Controlling Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Timer clock select register m (TPSm) • Timer mode register mn (TMRmn) • Timer status register mn (TSRmn) •...
Page 168: Peripheral Enable Register 0 (Per0)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 169: Timer Clock Select Register M (Tpsm)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1, CKm2, CKm3) that are commonly supplied to each channel. CKm0 is selected by using bits 3 to 0 of the TPSm register, and CKm1 is selected by using bits 7 to 4 of the TPSm register.
Page 170 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 10 Format of Timer clock select register m (TPSm) (1/2) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H Symbol PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm...
Page 171 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 11 Format of Timer clock select register m (TPSm) (2/2) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H Symbol PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm...
Page 172: Timer Mode Register Mn (Tmrmn)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock ), select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
Page 173 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 12 Format of Timer mode register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03), After reset: 0000H F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13) Symbol TMRmn MAST (n = 2)
Page 174 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 13 Format of Timer mode register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03), After reset: 0000H F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13) Symbol TMRmn MAST (n = 2)
Page 175 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 14 Format of Timer mode register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03), After reset: 0000H F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13) Symbol TMRmn MAST (n = 2)
Page 176 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 15 Format of Timer mode register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03), After reset: 0000H F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13) Symbol TMRmn MAST (n = 2)
Page 177: Timer Status Register Mn (Tsrmn)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B).
Page 178: Timer Channel Enable Status Register M (Tem)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.5 Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm).
Page 179: Timer Channel Start Register M (Tsm)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1.
Page 180 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Caution 1. Be sure to clear bits 15 to 12, 10, 8 to 4 to “0” Caution 2. When switching from a function that does not use TImn pin input to one that does, the following wait period is required from when timer mode register mn (TMRmn) is set until the TSmn (TSHm1, TSHm3) bit is set to 1.
Page 181: Timer Channel Stop Register M (Ttm)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0.
Page 182: Timer Input Select Register 0 (Tis0)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channels 0 and 1 of unit 0 timer input. The TIS0 register can be set by an 8-bit memory manipulation instruction.
Page 183: Timer Output Enable Register M (Toem)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.9 Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
Page 184: Timer Output Register M (Tom)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.10 Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel.
Page 185: Timer Output Level Register M (Tolm)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.11 Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1).
Page 186: Timer Output Mode Register M (Tomm)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.12 Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
Page 187: Noise Filter Enable Register 1 (Nfen1)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.13 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise...
Page 188 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 25 Format of Noise filter enable register 1 (NFEN1) Address: F0071H After reset: 00H Symbol NFEN1 TNFEN03 TNFEN01 TNFEN00 TNFEN03 Enable/disable using noise filter of TI03 pin input signal Noise filter OFF...
Page 189: Registers Controlling Port Functions Of Pins To Be Used For Timer I/O
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.3.14 Registers controlling port functions of pins to be used for timer I/O Using port pins for the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target pins (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)).
Page 190: Basic Rules Of Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Basic Rules of Timer Array Unit 7.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
Page 191 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave channels forming one simultaneous channel operation function). If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous channel operation function in 7.4.1 Basic rules of simultaneous channel operation function do not apply to the...
Page 192: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels.
Page 193: Operation Of Counter
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Operation of Counter 7.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCSmn bit of timer mode TCLK register mn (TMRmn). • Operation clock (f ) specified by the CKSmn0 and CKSmn1 bits •...
Page 194 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TImn pin and...
Page 195: Start Timing Of Counter
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 7 - 4.
Page 196: Operation Of Counter
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 197 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
Page 198 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 199 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected.
Page 200 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
Page 201: Channel Output (Tomn Pin) Control
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Channel Output (TOmn pin) Control 7.6.1 TOmn pin output circuit configuration Figure 7 - 33 Output Circuit Configuration <5> TOmn register Interrupt signal of the master channel (INTTMmn) TOmn pin Interrupt signal of the slave channel...
Page 202: Tomn Pin Output Setting
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.6.2 TOmn Pin Output Setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 7 - 34 Status Transition from Timer Output Setting to Operation Start...
Page 203: Cautions On Channel Output Operation
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.6.3 Cautions on Channel Output Operation (1) Changing values set in the registers TOm, TOEm, TOLm, and TOMm during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn...
Page 204 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
Page 205 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT When operation starts with slave channel output mode (TOMmn = 1) setting (PWM output)) When slave channel output mode (TOMmn = 1), the active level is determined by timer output level register m (TOLm) setting.
Page 206 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
Page 207 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 38 Set/Reset Timing Operating Statuses (1) Basic operation timing TCLK INTTMmn Master Internal reset channel signal TOmn pin/TOmn Toggle Toggle Internal reset signal 1 clock delay INTTMmp Slave channel Internal reset...
Page 208: Collective Manipulation Of Tomn Bit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
Page 209: Timer Interrupt And Tomn Pin Output At Operation Start
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.6.5 Timer Interrupt and TOmn Pin Output at Operation Start In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start.
Page 210: Timer Input (Timn) Control
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Timer Input (TImn) Control 7.7.1 TImn input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller.
Page 211: Cautions On Channel Input Operation
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.
Page 212: Independent Channel Operation Function Of Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Independent Channel Operation Function of Timer Array Unit 7.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
Page 213 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 42 Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 Note Operation clock Timer counter Output TOmn pin CKm0 register mn (TCRmn) controller Timer data Interrupt Interrupt signal TSmn register mn (TDRmn)
Page 214 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 44 Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1...
Page 215 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 45 Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Input clock supply for timer array unit m is stopped default (Clock supply is stopped and writing to each register setting is disabled.)
Page 216 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 46 Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TOmn pin output level stop Clears the TOmn bit to 0 after the value to be held is set to the port register.
Page 217: Operation As External Event Counter
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt.
Page 218 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 48 Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn 0000H 0003H 0002H TDRmn INTTMmn 4 events 4 events 3 events Remark 1. m: Unit number (m = 0), n: Channel number (n = 3) Remark 2.
Page 219 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 49 Example of Set Contents of Registers in External Event Counter Mode (1/2) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 C CSmn S TSmn2 STSmn1 S TSmn0 CISmn1 CISmn0 MDmn3 M Dmn2...
Page 220 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 50 Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Input clock supply for timer array unit m is stopped default (Clock supply is stopped and writing to each register setting is disabled.)
Page 221: Operation As Input Pulse Interval Measurement
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.8.3 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit is set to 1.
Page 222 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 52 Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Remark 1. m: Unit number (m = 0), n: Channel number (n = 3) Remark 2.
Page 223 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 53 Example of Set Contents of Registers to Measure Input Pulse Interval Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 C ISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn...
Page 224 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Remark m: Unit number (m = 0), n: Channel number (n = 3) Figure 7 - 54 Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Input clock supply for timer array unit m is stopped...
Page 225: Operation As Input Signal High-/Low-Level Width Measurement
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.8.4 Operation as input signal high-/low-level width measurement Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control register (ISC) to 1. In the following descriptions, read TImn as RxD0.
Page 226 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 55 Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CKm1 Note Operation clock Timer counter CKm0 register mn (TCRmn) TNFENxx Noise Edge Timer data Interrupt Interrupt signal TImn pin...
Page 227 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 57 Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn...
Page 228 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 58 Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Input clock supply for timer array unit m is stopped default (Clock supply is stopped and writing to each register setting is disabled.)
Page 229: Operation As Delay Counter
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.8.5 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval.
Page 230 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 60 Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn INTTMmn a + 1 b + 1 Remark 1. m: Unit number (m = 0), n: Channel number (n = 3) Remark 2.
Page 231 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 61 Example of Set Contents of Registers to Delay Counter Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn Note Operation mode of channel n...
Page 232 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 62 Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Input clock supply for timer array unit m is stopped default (Clock supply is stopped and writing to each register setting is disabled.)
Page 233: Simultaneous Channel Operation Function Of Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Simultaneous Channel Operation Function of Timer Array Unit 7.9.1 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
Page 234 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 63 Block Diagram of Operation as PWM Function Master channel (interval timer mode) CKm1 Operation clock Timer counter CKm0 register mn (TCRmn) Timer data Interrupt signal Interrupt TSmn register mn (TDRmn)
Page 235 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 64 Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH TCRmn Master 0000H channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp 0000H Slave channel TDRmp TOmp INTTMmp a + 1...
Page 236 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 65 Example of Set Contents of Registers When PWM Function (Master Channel) Is Used Timer mode register mn (TMRmn) TERmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1...
Page 237 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 66 Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used Timer mode register mp (TMRmp) CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0...
Page 238 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 67 Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Input clock supply for timer array unit m is stopped default (Clock supply is stopped and writing to each register setting is disabled.)
Page 239 RL78/G1H CHAPTER 7 TIMER ARRAY UNIT Figure 7 - 68 Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer...
Page 240: Cautions When Using Timer Array Unit
RL78/G1H CHAPTER 7 TIMER ARRAY UNIT 7.10 Cautions When Using Timer Array Unit 7.10.1 Cautions When Using Timer output Depends on products, a pin is assigned a timer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status.
Page 241: Timer Rj
RL78/G1H CHAPTER 8 TIMER RJ CHAPTER 8 TIMER RJ Functions of Timer RJ Timer RJ is a 16-bit timer. This 16-bit timer consists of a reload register and a down counter. The reload register and the down counter are allocated to the same address, and they can be accessed by accessing the TRJ0 register.
Page 242: Configuration Of Timer Rj
RL78/G1H CHAPTER 8 TIMER RJ Configuration of Timer RJ Figure 8 - 1 shows the Timer RJ Block Diagram. Figure 8 - 1 Timer RJ Block Diagram TCK2∼TCK0 = 000B = 001B = 011B = 100B Note = 101B Event input from ELC...
Page 243: Registers Controlling Timer Rj
RL78/G1H CHAPTER 8 TIMER RJ Registers Controlling Timer RJ Table 8 - 2 lists the Registers Controlling Timer RJ. Table 8 - 2 Registers Controlling Timer RJ Register Name Symbol Peripheral enable register 1 PER1 Subsystem clock supply mode control register...
Page 244: Peripheral Enable Register 1 (Per1)
RL78/G1H CHAPTER 8 TIMER RJ 8.3.1 Peripheral enable register 1 (PER1) The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
Page 245: Subsystem Clock Supply Mode Control Register (Osmc)
RL78/G1H CHAPTER 8 TIMER RJ 8.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the timer RJ operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
Page 246: Timer Rj Counter Register 0 (Trj0)
RL78/G1H CHAPTER 8 TIMER RJ 8.3.3 Timer RJ counter register 0 (TRJ0) TRJ0 is a 16-bit register. The write value is written to the reload register and the read value is read from the counter. The states of the reload register and the counter are changed depending on the TSTART bit in the TRJCR0 register.
Page 247: Timer Rj Control Register 0 (Trjcr0)
RL78/G1H CHAPTER 8 TIMER RJ 8.3.4 Timer RJ control register 0 (TRJCR0) The TRJCR0 register starts or stops count operation and indicates the status of timer RJ. The TRJCR0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 248: Timer Rj Mode Register 0 (Trjmr0)
RL78/G1H CHAPTER 8 TIMER RJ 8.3.5 Timer RJ mode register 0 (TRJMR0) The TRJMR0 register sets the operating mode of timer RJ. The TRJMR0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 249: Timer Rj Operation
RL78/G1H CHAPTER 8 TIMER RJ Timer RJ Operation 8.4.1 Reload Register and Counter Rewrite Operation Regardless of the operating mode, the timing of the rewrite operation to the reload register and the counter differs depending on the value in the TSTART bit in the TRJCR0 register. When the TSTART bit is 0 (count stops), the count value is directly written to the reload register and the counter.
Page 250: Timer Mode
RL78/G1H CHAPTER 8 TIMER RJ 8.4.2 Timer Mode In this mode, the counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR0 register. In timer mode, the count value is decremented by 1 each time the count source is input. When the count value reaches 0000H and the next count source is input, an underflow occurs and an interrupt request is generated.
Page 251: Coordination With Event Link Controller (Elc)
RL78/G1H CHAPTER 8 TIMER RJ 8.4.3 Coordination with Event Link Controller (ELC) Through coordination with the ELC, event input from the ELC can be set to be the count source. Bits TCK0 to TCK2 in the TRJMR0 register count at the rising edge of event input from the ELC. However, ELC input does not function in event counter mode.
Page 252: Cautions For Timer Rj
RL78/G1H CHAPTER 8 TIMER RJ Cautions for Timer RJ 8.5.1 Count Operation Start and Stop Control • When the count source is set to other than the ELC After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF bit in the TRJCR0 register remains 0 (count stops) for three cycles of the count source.
Page 253: When Timer Rj Operating Clock Is Stopped
RL78/G1H CHAPTER 8 TIMER RJ 8.5.5 When Timer RJ Operating Clock is Stopped Supplying or stopping the timer RJ clock can be controlled by the TRJ0EN bit in the PER1 register. Note that the following SFRs cannot be accessed while the timer RJ clock is stopped. Make sure the timer RJ clock is supplied before accessing any of these registers.
Page 254: Real-Time Clock
RL78/G1H CHAPTER 9 REAL-TIME CLOCK CHAPTER 9 REAL-TIME CLOCK Functions of Real-time Clock The real-time clock has the following features. • Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. • Constant-period interrupt function (period: 0.5 seconds, 1 second, 1 minute, 1 hour, 1 day, 1 month) •...
Page 255 RL78/G1H CHAPTER 9 REAL-TIME CLOCK Figure 9 - 1 Block Diagram of Real-time Clock Real-time clock control register 1 Real-time clock control register 0 Subsystem clock supply mode WUTMM WALE WALIE WAFG RIFG RWST RWAIT RTCE AMPM control register (OSMC)
Page 256: Registers Controlling Real-Time Clock
RL78/G1H CHAPTER 9 REAL-TIME CLOCK Registers Controlling Real-time Clock The real-time clock is controlled by the following registers. • Peripheral enable register 0 (PER0) • Subsystem clock supply mode control register (OSMC) • Real-time clock control register 0 (RTCC0) • Real-time clock control register 1 (RTCC1) •...
Page 257: Peripheral Enable Register 0 (Per0)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 258: Subsystem Clock Supply Mode Control Register (Osmc)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the real-time clock count clock (f In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
Page 259: Real-Time Clock Control Register 0 (Rtcc0)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.3 Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, and set a 12- or 24-hour system and the constant-period interrupt function.
Page 260: Real-Time Clock Control Register 1 (Rtcc1)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.4 Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 261 RL78/G1H CHAPTER 9 REAL-TIME CLOCK Figure 9 - 6 Format of Real-time clock control register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag Fixed-cycle interrupt is not generated. Fixed-cycle interrupt is generated. This flag indicates the status of generation of the fixed-cycle interrupt. When the fixed-cycle interrupt is generated, it is set to “1”.
Page 262: Second Count Register (Sec)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.5 Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the internal counter (16-bit) overflows.
Page 263: Hour Count Register (Hour)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.7 Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours.
Page 264 RL78/G1H CHAPTER 9 REAL-TIME CLOCK Table 9 - 2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 9 - 2 Displayed Time Digits 24-Hour Display (AMPM = 1)
Page 265: Day Count Register (Day)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.8 Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows.
Page 266: Week Count Register (Week)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.9 Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter.
Page 267: Month Count Register (Month)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.10 Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows.
Page 268: Watch Error Correction Register (Subcud)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.12 Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the internal counter (16-bit) to the second count register (SEC) (reference value: 7FFFH).
Page 269: Alarm Minute Register (Alarmwm)
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.3.13 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code.
Page 270 RL78/G1H CHAPTER 9 REAL-TIME CLOCK Here is an example of setting the alarm. 12-Hour Display 24-Hour Display Hour Hour Minute Minute Hour Hour Minute Minute Wednes Sunday Monday Tuesday Thursday Friday Saturday Time of Alarm Every day, 0:00 a.m. Every day, 1:30 a.m.
Page 271: Real-Time Clock Operation
RL78/G1H CHAPTER 9 REAL-TIME CLOCK Real-time Clock Operation 9.4.1 Starting operation of real-time clock Figure 9 - 18 Procedure for Starting Operation of Real-time Clock Start Note 1 RTCEN = 1 Supplies input clock. RTCE = 0 Stops counter operation.
Page 272: Shifting To Halt/Stop Mode After Starting Operation
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after INTRTC interrupt has occurred.
Page 273: Reading/Writing Real-Time Clock
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. Figure 9 - 20 Procedure for Reading Real-time Clock Start Stops SEC to YEAR counters.
Page 274 RL78/G1H CHAPTER 9 REAL-TIME CLOCK Figure 9 - 21 Procedure for Writing Real-time Clock Start Stops SEC to YEAR counters. RWAIT = 1 Mode to read and write count values RWST = 1? Checks wait status of counter. Writing SEC Writes second count register.
Page 275: Setting Alarm Of Real-Time Clock
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE (alarm operation invalid) first. Figure 9 - 22 Alarm Setting Procedure Start WALE = 0 Match operation of alarm is invalid.
Page 276: Example Of Watch Error Correction Of Real-Time Clock
RL78/G1H CHAPTER 9 REAL-TIME CLOCK 9.4.5 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the internal counter (16-bit) is calculated by using the following expression.
Page 277 RL78/G1H CHAPTER 9 REAL-TIME CLOCK Correction example Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz - 131.2 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 32.768 kHz from the PCLBUZ0 pin.
Page 278 RL78/G1H CHAPTER 9 REAL-TIME CLOCK Figure 9 - 23 Correction Operation when (DEV, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 1, 0, 1, 1, 0, 0) R01UH0575EJ0120 Rev. 1.20 Page 260 of 920 Dec 22, 2016...
Page 279: Bit Interval Timer
RL78/G1H CHAPTER 10 12-BIT INTERVAL TIMER CHAPTER 10 12-BIT INTERVAL TIMER 10.1 Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter’s SNOOZE mode.
Page 280: Registers Controlling 12-Bit Interval Timer
RL78/G1H CHAPTER 10 12-BIT INTERVAL TIMER 10.3 Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0) • Subsystem clock supply mode control register (OSMC) • 12-bit interval timer control register (ITMC) 10.3.1...
Page 281: Subsystem Clock Supply Mode Control Register (Osmc)
RL78/G1H CHAPTER 10 12-BIT INTERVAL TIMER 10.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the 12-bit interval timer, real-time clock, and timer RJ operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
Page 282: 12-Bit Interval Timer Control Register (Itmc)
RL78/G1H CHAPTER 10 12-BIT INTERVAL TIMER 10.3.3 12-bit interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction.
Page 283: 12-Bit Interval Timer Operation
RL78/G1H CHAPTER 10 12-BIT INTERVAL TIMER 10.4 12-bit Interval Timer Operation 10.4.1 12-bit interval timer operation timing The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate an 12-bit interval timer that repeatedly generates interrupt requests (INTIT).
Page 284: Start Of Count Operation And Re-Enter To Halt/Stop Mode After Returned From Halt/Stop Mode
RL78/G1H CHAPTER 10 12-BIT INTERVAL TIMER 10.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Page 285: Clock Output/Buzzer Output Controller
RL78/G1H CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency.
Page 286 RL78/G1H CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 11 - 1 Block Diagram of Clock Output/Buzzer Output Controller Internal bus Clock output select register 1 (CKS1) CSEL1 CCS12 CCS11 CCS10 PCLOE1 Prescaler MAIN PCLOE1 to f MAIN MAIN Clock/buzzer to f...
Page 287: Configuration Of Clock Output/Buzzer Output Controller
RL78/G1H CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 11 - 1 Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select registers n (CKSn)
Page 288 RL78/G1H CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 11 - 2 Format of Clock output select registers n (CKSn) <R> Address: FFFA5H (CKS0), FFFA6H (CKS1) After reset: 00H Symbol <7> CKSn PCLOEn CSELn CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZn pin output enable/disable specification...
Page 289: Registers Controlling Port Functions Of Pins To Be Used For Clock Or Buzzer Output
RL78/G1H CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.3.2 Registers controlling port functions of pins to be used for clock or buzzer output Using a port pin for clock or buzzer output requires setting of the registers that control the port functions multiplexed on the target pin (port mode register (PMxx), port register (Pxx)).
Page 290: Operations Of Clock Output/Buzzer Output Controller
RL78/G1H CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
Page 291: Watchdog Timer
RL78/G1H CHAPTER 12 WATCHDOG TIMER CHAPTER 12 WATCHDOG TIMER 12.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. The watchdog timer operates on the low-speed on-chip oscillator clock (f The counting operation of the watchdog timer is set by the option byte (000C0H).
Page 292: Configuration Of Watchdog Timer
RL78/G1H CHAPTER 12 WATCHDOG TIMER 12.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 12 - 1 Configuration of Watchdog Timer Item Configuration Counter Internal counter (17 bits) Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.
Page 293: Register Controlling Watchdog Timer
RL78/G1H CHAPTER 12 WATCHDOG TIMER 12.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 12.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
Page 294: Operation Of Watchdog Timer
RL78/G1H CHAPTER 12 WATCHDOG TIMER 12.4 Operation of Watchdog Timer 12.4.1 Controlling operation of watchdog timer (1) When the watchdog timer is used, its operation is specified by the option byte (000C0H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 26).
Page 295: Setting Overflow Time Of Watchdog Timer
RL78/G1H CHAPTER 12 WATCHDOG TIMER Caution 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). Status WDSTBYON = 0...
Page 296: Setting Window Open Period Of Watchdog Timer
RL78/G1H CHAPTER 12 WATCHDOG TIMER 12.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows.
Page 297: Setting Watchdog Timer Interval Interrupt
RL78/G1H CHAPTER 12 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Timing Setting of Window Open Period 100% Window close time 0 to 20.08 ms 0 to 10.04 ms...
Page 298: A/D Converter
RL78/G1H CHAPTER 13 A/D CONVERTER CHAPTER 13 A/D CONVERTER 13.1 Function of A/D Converter The A/D converter is a converter that converts analog input signals into digital values, and 10-bit or 8-bit resolution can be selected by the ADTYP bit of the A/D converter mode register 2 (ADM2).
Page 299 RL78/G1H CHAPTER 13 A/D CONVERTER Various A/D conversion modes can be specified by using the mode combinations below. Trigger mode Software trigger Conversion is started by software. Hardware trigger no-wait mode Conversion is started by detecting a hardware trigger. Hardware trigger wait mode...
Page 300 RL78/G1H CHAPTER 13 A/D CONVERTER Figure 13 - 1 Block Diagram of A/D Converter Selector Selector Selector Digital port control Digital port control R01UH0575EJ0120 Rev. 1.20 Page 282 of 920 Dec 22, 2016...
Page 301: Configuration Of A/D Converter
RL78/G1H CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI2, ANI13, ANI14, and ANI19 pins These are the analog input pins of the six channels of the A/D converter. They input analog signals to be converted into digital signals.
Page 302 RL78/G1H CHAPTER 13 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
Page 303: Registers Controlling A/D Converter
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3 Registers Controlling A/D Converter The A/D converter is controlled by the following registers. • Peripheral enable register 0 (PER0) • A/D converter mode register 0 (ADM0) • A/D converter mode register 1 (ADM1) • A/D converter mode register 2 (ADM2) •...
Page 304: Peripheral Enable Register 0 (Per0)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 305: A/D Converter Mode Register 0 (Adm0)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 306 RL78/G1H CHAPTER 13 A/D CONVERTER Table 13 - 1 Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Conversion stopped state Conversion standby state Setting prohibited Conversion-in-progress state Table 13 - 2 Setting and Clearing Conditions for ADCS Bit...
Page 307 RL78/G1H CHAPTER 13 A/D CONVERTER Note 2. The following time is the maximum amount of time necessary to start conversion. ADM0 Conversion Start Time (Number of f Clocks) Conversion Clock Software trigger mode/ Hardware trigger wait mode Hardware trigger no wait mode For the second and subsequent conversion in sequential conversion mode, the stabilization wait time for A/D power supply do not occur in hardware trigger wait mode.
Page 308 RL78/G1H CHAPTER 13 A/D CONVERTER Table 13 - 3 A/D Conversion Time Selection (1/4) (1) When there is no A/D power supply stabilization wait time Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Mode Conversion...
Page 309 RL78/G1H CHAPTER 13 A/D CONVERTER Table 13 - 4 A/D Conversion Time Selection (2/4) (2) When there is no A/D power supply stabilization wait time Low-voltage mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Mode Conversion...
Page 310 RL78/G1H CHAPTER 13 A/D CONVERTER Table 13 - 5 A/D Conversion Time Selection (3/4) (3) When there is A/D power supply stabilization wait time Normal mode 1, 2 Note 1 (hardware trigger wait mode A/D Converter Mode Mode Conversion Number of...
Page 311 RL78/G1H CHAPTER 13 A/D CONVERTER Table 13 - 6 A/D Conversion Time Selection (4/4) (4) When there is A/D power supply stabilization wait time Low-voltage mode 1, 2 Note 1 (hardware trigger wait mode A/D Converter Mode Mode Conversion Number of...
Page 312 RL78/G1H CHAPTER 13 A/D CONVERTER Figure 13 - 5 A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) 1 is written to ADCS or ADS is rewritten. ADCS Sampling timing INTAD Conversion Sampling Successive conversion Sampling Successive conversion...
Page 313: A/D Converter Mode Register 1 (Adm1)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 314: A/D Converter Mode Register 2 (Adm2)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.4 A/D converter mode register 2 (ADM2) This register is used to select the + side or - side reference voltage of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode.
Page 315 RL78/G1H CHAPTER 13 A/D CONVERTER Figure 13 - 8 Format of A/D converter mode register 2 (ADM2) (2/2) Address: F0010H After reset: 00H Symbol <3> <2> <0> ADM2 ADREFP0 ADREFM ADRCK ADTYP ADRCK Checking the upper limit and lower limit conversion result values The interrupt signal (INTAD) is output when the ADLL register ≤...
Page 316: 10-Bit A/D Conversion Result Register (Adcr)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.5 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR).
Page 317: Analog Input Channel Specification Register (Ads)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 318: Conversion Result Comparison Upper Limit Setting Register (Adul)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 13 - 9).
Page 319: A/D Test Register (Adtes)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage or - side reference voltage for the converter, an analog input channel as the target for A/D conversion. When using this register to test the converter, set as follows.
Page 320: 13.3.11 Registers Controlling Port Function Of Analog Input Pins
RL78/G1H CHAPTER 13 A/D CONVERTER 13.3.11 Registers controlling port function of analog input pins Set up the registers for controlling the functions of the ports shared with the analog input pins of the A/D converter (port mode registers (PMxx), port mode control registers (PMCxx), and A/D port configuration register (ADPC)).
Page 321: A/D Converter Conversion Operations
RL78/G1H CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
Page 322 RL78/G1H CHAPTER 13 A/D CONVERTER Figure 13 - 16 Conversion Operation of A/D Converter (Software Trigger Mode) 1 is written to ADCS ADCS Conversion time Conversion Sampling start time time A/D converter Conversion Conversion A/D conversion Conversion start Sampling operation...
Page 323: Input Voltage And Conversion Results
RL78/G1H CHAPTER 13 A/D CONVERTER 13.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 324: A/D Converter Operation Modes
RL78/G1H CHAPTER 13 A/D CONVERTER 13.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 13.7 A/D Converter Setup Flowchart. 13.6.1 Software trigger mode (select mode, sequential conversion mode) <1>...
Page 325: Software Trigger Mode (Select Mode, One-Shot Conversion Mode)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 326: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.6.3 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 327: Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.6.4 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <R> <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 328: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.6.5 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 329: Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
RL78/G1H CHAPTER 13 A/D CONVERTER 13.6.6 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 330: A/D Converter Setup Flowchart
RL78/G1H CHAPTER 13 A/D CONVERTER 13.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. 13.7.1 Setting up software trigger mode Figure 13 - 24 Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 331: Setting Up Hardware Trigger No-Wait Mode
RL78/G1H CHAPTER 13 A/D CONVERTER 13.7.2 Setting up hardware trigger no-wait mode Figure 13 - 25 Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 332: Setting Up Hardware Trigger Wait Mode
RL78/G1H CHAPTER 13 A/D CONVERTER 13.7.3 Setting up hardware trigger wait mode Figure 13 - 26 Setting up Hardware Trigger Wait Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 333: Setting Up Test Mode
RL78/G1H CHAPTER 13 A/D CONVERTER 13.7.4 Setting up test mode Figure 13 - 27 Setting up Test Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. • ADM0 register •...
Page 334: Snooze Mode Function
RL78/G1H CHAPTER 13 A/D CONVERTER 13.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger.
Page 335 RL78/G1H CHAPTER 13 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
Page 336 RL78/G1H CHAPTER 13 A/D CONVERTER Figure 13 - 29 Flowchart for Setting up SNOOZE Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.
Page 337: Cautions For A/D Converter
RL78/G1H CHAPTER 13 A/D CONVERTER 13.9 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
Page 338 RL78/G1H CHAPTER 13 A/D CONVERTER (5) Analog input (ANIn) pins <1> The analog input pins are also used as input port pins. When A/D conversion is performed with any of the ANI0 to ANI2, ANI13, ANI14, and ANI19 pins selected, do not change to output value P20 to P22, P120, P155, and P156 while conversion is in progress;...
Page 339 RL78/G1H CHAPTER 13 A/D CONVERTER Figure 13 - 31 Timing of A/D Conversion End Interrupt Request Generation ADS rewrite ADS rewrite ADIF is set but ANIm conversion (start of ANIn conversion) (start of ANIm conversion) has not ended. A/D conversion...
Page 340 RL78/G1H CHAPTER 13 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13 - 32 Internal Equivalent Circuit of ANIn Pin ANIn Table 13 - 7 Resistance and Capacitance Values of Equivalent Circuit (Reference Values) ANIn Pins R1 [k Ω...
Page 341: Serial Array Unit
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT CHAPTER 14 SERIAL ARRAY UNIT Serial array unit can achieve communication functions of 3-wire serial (CSI) and UART. Function assignment of each channel is as shown below. Unit Channel Used as CSI Used as UART...
Page 342: Functions Of Serial Array Unit
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.1 Functions of Serial Array Unit Each serial interface has the following features. 14.1.1 3-wire serial I/O (CSIp) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
Page 343: Uart (Uartq)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.1.2 UART (UARTq) This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 344: Configuration Of Serial Array Unit
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 14 - 1 Configuration of Serial Array Unit Item Configuration Shift register 8 bits Buffer register Note 1 Lower 8 bits of serial data register mn (SDRmn)
Page 345 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 1 shows the Block Diagram of Serial Array Unit 0. Figure 14 - 1 Block Diagram of Serial Array Unit 0 Serial output register 0 (SO0) Noise filter enable register 0 (NFEN0)
Page 346 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 2 shows the Block Diagram of Serial Array Unit 1. Figure 14 - 2 Block Diagram of Serial Array Unit 1 Serial output register 1 (SO1) Noise filter enable register 0 (NFEN0)
Page 347: Shift Register
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.2.1 Shift register This is an 8-bit register that converts parallel data into serial data or vice versa. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin.
Page 348 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 3 Format of Serial data register mn (SDRmn) (mn = 02, 03, 10, 11, 12, 13) Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), After reset: 0000H FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
Page 349: Registers Controlling Serial Array Unit
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. Caution In this chapter, read all the registers of the channels that are not available as the reserved registers.
Page 350: Peripheral Enable Register 0 (Per0)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 351: Serial Clock Select Register M (Spsm)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0.
Page 352 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 5 Format of Serial clock select register m (SPSm) Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H Symbol SPSm Note Section of operation clock (CKmk) 2 MHz 5 MHz...
Page 353: Serial Mode Register Mn (Smrmn)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (f ), specify whether the serial clock (f ) may be input or not, set a start trigger, an operation mode (CSI or UART), and an interrupt source.
Page 354: Serial Communication Operation Setting Register Mn (Scrmn)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 7 Format of Serial mode register mn (SMRmn) (2/2) Address: F0114H, F0115H (SMR02), F0116H, F0117H (SMR03), After reset: 0020H F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13) Symbol SMRmn Note Note Controls inversion of level of receive data of channel n in UART mode Note Falling edge is detected as the start bit.
Page 355 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 8 Format of Serial communication operation setting register mn (SCRmn) (1/2) Address: F011CH, F011DH (SCR02), F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10)to F015EH, F015FH (SCR13) Symbol SCRmn Note 1 Setting of operation mode of channel n Disable communication.
Page 356 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 9 Format of Serial communication operation setting register mn (SCRmn) (2/2) Address: F011CH, F011DH (SCR02), F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13) Symbol SCRmn Note 1...
Page 357: Serial Data Register Mn (Sdrmn)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.5 Serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as...
Page 358: Serial Flag Clear Trigger Register Mn (Sirmn)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.
Page 359: Serial Status Register Mn (Ssrmn)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error.
Page 360 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 13 Format of Serial status register mn (SSRmn) (2/2) Address: F0104H, F0105H (SSR02), F0106H, F0107H (SSR03), After reset: 0000H F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13) Symbol SSRmn Note Framing error detection flag of channel n Note No error occurs.
Page 361: Serial Channel Start Register M (Ssm)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).
Page 362: Serial Channel Stop Register M (Stm)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).
Page 363: Serial Channel Enable Status Register M (Sem)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
Page 364: Serial Output Enable Register M (Soem)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
Page 365: Serial Output Register M (Som)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
Page 366: Serial Output Level Register M (Solm)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.13 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode.
Page 367 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 20 Examples of Reverse Transmit Data Non-reverse Output (SOLmn = 0) SOLm = 0 output SOUT0n Transmit data Reverse Output (SOLmn = 1) SOLm = 1 output SOUT0n Transmit data (inverted) R01UH0575EJ0120 Rev.
Page 368: Noise Filter Enable Register 0 (Nfen0)
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.14 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.
Page 369: 14.3.15 Registers Controlling Port Functions Of Serial Input/Output Pins
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.3.15 Registers controlling port functions of serial input/output pins Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port input mode register (PIMxx), port output mode register (POMxx), port mode control register (PMCxx)).
Page 370: Operation Stop Mode
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode.
Page 371: Stopping The Operation By Channels
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 14 - 23 Each Register Setting When Stopping the Operation by Channels Serial channel stop register m (STm)...
Page 372: Operation Of 3-Wire Serial I/O (Csip) Communication
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5 Operation of 3-Wire Serial I/O (CSIp) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] • Data length of 7 or 8 bits •...
Page 373 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSIp) are channel 2 of SAU0 and channels 0 to 2 of SAU1. Unit Channel Used as CSI Used as UART Cannot be used Cannot be used CSI10...
Page 374: Master Transmission
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.1 Master transmission Master transmission is that the RL78 microcontroller outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI10 CSI20 CSI21 CSI30 Target channel Channel 2 of SAU0 Channel 0 of SAU1...
Page 375 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 24 Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSIp) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 376 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 25 Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 377 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 27 Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation completed. (Essential) Slave ready? Disable data output and clock output of the target...
Page 378 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 14 - 28 Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
Page 379 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 29 Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting Note Set data for transmission and the number of data. Clear communication end flag Setting transmit data...
Page 380 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 14 - 30 Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <6> STmn SEmn SDRmn...
Page 381 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 31 Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting Note Set data for transmission and the number of data . Clear communication end flag Setting transmit data...
Page 382: Master Reception
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.2 Master reception Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI10 CSI20 CSI21 CSI30 Target channel Channel 2 of SAU0 Channel 0 of SAU1...
Page 383 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 32 Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSIp) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 384 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 33 Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 385 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 35 Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation completed. (Essential) Completing slave preparations? Disable clock output of the target channel by...
Page 386 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 14 - 36 Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2...
Page 387 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 37 Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication SAU default setting Note Setting storage area of the receive data, number of communication data Setting receive data (Storage area, Reception data pointer, Number of communication data and...
Page 388 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Processing flow (in continuous reception mode) Figure 14 - 38 Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 389 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 39 Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication SAU default setting Note <1> Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, Number of...
Page 390: Master Transmission/Reception
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.3 Master transmission/reception Master transmission/reception is that the RL78 microcontroller outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI10 CSI20 CSI21 CSI30 Target channel Channel 2 of SAU0 Channel 0 of SAU1...
Page 391 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 40 Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSIp) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 392 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 41 Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 393 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 43 Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or Completing slave communication operation completed. (Essential) preparations? Disable data output and clock output of the target...
Page 394 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 14 - 44 Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2...
Page 395 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 45 Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication SAU default setting Note Setting storage data and number of data for transmission /reception data Setting (Storage area, Transmission data pointer, Reception data pointer,...
Page 396 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 14 - 46 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 397 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 47 Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting SAU default setting Note <1> Setting storage data and number of data for transmission/reception data Setting (Storage area, Transmission data pointer, Reception data, Number...
Page 398: Slave Transmission
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.4 Slave transmission Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI10 CSI21 CSI30 Target channel...
Page 399 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 48 Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSIp) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 400 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 49 Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 401 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 51 Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target (master) Completing master or operation completed. (Essential) preparations? Disable data output of the target channel by setting...
Page 402 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 14 - 52 Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
Page 403 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 53 Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting Note Set storage area and the number of data for transmit data (Storage area, Transmission data pointer, Number of...
Page 404 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Processing flow (in continuous transmission mode) Figure 14 - 54 Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <6> STmn SEmn SDRmn Transmit data 2...
Page 405 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 55 Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting Note SAU default setting <1> Set storage area and the number of data for transmit data (Storage area, Transmission data pointer, Number of communication...
Page 406: Slave Reception
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.5 Slave reception Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI10 CSI21 CSI30 Target channel...
Page 407 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 56 Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSIp) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 408 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 57 Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 409 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 59 Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) Completing master or operation completed. (Essential) preparations? Disable clock output of the target channel by...
Page 410 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 14 - 60 Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1...
Page 411 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 61 Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication SAU default setting Note Clear storage area setting and the number of receive data (Storage area, Reception data pointer, Number of communication...
Page 412: Slave Transmission/Reception
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.6 Slave transmission/reception Slave transmission/reception is that the RL78 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI10 CSI21 CSI30 Target channel...
Page 413 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 62 Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSIp) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 414 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 63 Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 415 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 65 Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target (master) Completing master or operation completed. (Essential) preparations? Disable data output of the target channel by setting...
Page 416 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 14 - 66 Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2...
Page 417 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 67 Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication SAU default setting Note Setting storage area and number of data for transmission/reception data Setting (Storage area, Transmission/reception data pointer, Number of communication...
Page 418 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 14 - 68 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 419 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 69 Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting Note Setting storage area and number of data for transmission/reception data Setting (Storage area, Transmission/reception data pointer, Number of...
Page 420: Calculating Transfer Clock Frequency
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.7 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSIp) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]...
Page 421 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Table 14 - 2 Selection of Operation Clock For 3-Wire Serial I/O SMRmn SPSm Register Note Operation Clock (f Register CKSmn = 32 MHz × × × × 32 MHz × × × ×...
Page 422: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O (Csip) Communication
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSIp) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSIp) communication is described in Figure 14 - 70. Figure 14 - 70 Processing Procedure in Case of Overrun Error...
Page 423: Operation Of Uart (Uartq) Communication
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.6 Operation of UART (UARTq) Communication This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 424: Uart Transmission
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.6.1 UART transmission UART transmission is an operation to transmit data from the RL78 microcontroller to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
Page 425 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 71 Example of Contents of Registers for UART Transmission of UART (UARTq) (1/2) Serial mode register mn (SMRmn) CKSmn CCSmn MDmn1 MDmn0 SMRmn Operation clock (f ) of channel n...
Page 426 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 72 Example of Contents of Registers for UART Transmission of UART (UARTq) (2/2) Serial output register m (SOm)... Sets only the bits of the target channel. CKOm3 CKOm2 CKOm1 CKOm0 SOm3...
Page 427 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 73 Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 428 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 75 Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target or Completing master communication operation completed (Essential) preparations? Disable data output of the target channel by setting...
Page 429 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 14 - 76 Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1...
Page 430 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 77 Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, refer to Figure 14 - 73. SAU default setting (Select transfer end interrupt) Set data for transmission and the number of data . Clear...
Page 431 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 14 - 78 Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SSmn <6> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3...
Page 432 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 79 Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication <1> For the initial setting, refer to Figure 14 - 73. SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data . Clear communication end flag...
Page 433: Uart Reception
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.6.2 UART reception UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
Page 434 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (1) Register setting Figure 14 - 80 Example of Contents of Registers for UART Reception of UART (UARTq) (1/2) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 435 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 81 Example of Contents of Registers for UART Reception of UART (UARTq) (2/2) Serial output register m (SOm)... The register that not used in this mode. CKOm3 CKOm2 CKOm1 CKOm0 SOm3...
Page 436 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Operation procedure Figure 14 - 82 Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 437 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 84 Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait until Completing communication completes its communication operation. (Essential) target preparations? Re-set the register to change the operation clock...
Page 438 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Processing flow Figure 14 - 85 Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 RxDq pin Receive data 1 Receive data 2 Receive data 3...
Page 439 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Figure 14 - 86 Flowchart of UART Reception Starting UART communication For the initial setting, refer to Figure 14 - 82. SAU default setting (setting to mask for error interrupt) Setting storage area of the receive data , number of communication data...
Page 440: Calculating Baud Rate
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.6.3 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UARTq) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
Page 441 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT Table 14 - 3 Selection of Operation Clock For UART SMRmn SPSm Register Note Operation Clock (f Register CKSmn = 32 MHz × × × × 32 MHz × × × × 16 MHz ×...
Page 442 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UARTq) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 443 RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UARTq) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 444: Procedure For Processing Errors That Occurred During Uart (Uartq) Communication
RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT 14.6.4 Procedure for processing errors that occurred during UART (UARTq) communication The procedure for processing errors that occurred during UART (UARTq) communication is described in Figures 14 - 88 and 14 - 89. Figure 14 - 88 Processing Procedure in Case of Parity Error or Overrun Error...
Page 445: Serial Interface Iica
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA CHAPTER 15 SERIAL INTERFACE IICA 15.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
Page 446 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 1 Block Diagram of Serial Interface IICA (channel 0) Internal bus IICA status register 0 (IICS0) WUP0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 00 Controller for...
Page 447 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 2 shows a serial bus configuration example. Figure 15 - 2 Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU2 Master CPU1 SDAAn SDAAn Slave CPU1 Slave CPU2...
Page 448: Configuration Of Serial Interface Iica
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 15 - 1 Configuration of Serial Interface IICA Item Configuration Registers IICA shift register n (IICAn) Slave address register n (SVAn)
Page 449 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (2) Slave address register n (SVAn) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVAn register can be set by an 8-bit memory manipulation instruction.
Page 450 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (9) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (10) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
Page 451: Registers Controlling Serial Interface Iica
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following eight registers. • Peripheral enable register 0 (PER0) • IICA control register n0 (IICCTLn0) • IICA flag register n (IICFn) •...
Page 452: Peripheral Enable Register 0 (Per0)
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 453 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 6 Format of IICA control register n0 (IICCTLn0) (1/4) Address: F0230H (IICCTL00), F0238H (IICCTL10) After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTLn0 IICEn LRELn WRELn SPIEn...
Page 454 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 7 Format of IICA control register n0 (IICCTLn0) (2/4) SPIEn Enable/disable generation of interrupt request when stop condition is detected Note 1 Disable Enable If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn =...
Page 455 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 8 Format of IICA control register n0 (IICCTLn0) (3/4) STTn Start condition trigger Notes 1, 2 Do not generate a start condition. When bus is released (in standby state, when IICBSYn = 0): If this bit is set (1), a start condition is generated (startup as the master).
Page 456 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 9 Format of IICA control register n0 (IICCTLn0) (4/4) Stop condition trigger Note SPTn Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing •...
Page 457: Iica Status Register N (Iicsn)
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.3.3 IICA status register n (IICSn) This register indicates the status of I The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the wait period.
Page 458 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 11 Format of IICA status register n (IICSn) (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) •...
Page 459: Iica Flag Register N (Iicfn)
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 12 Format of IICA status register n (IICSn) (3/3) ACKDn Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1) •...
Page 460 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 13 Format of IICA flag register n (IICFn) Note Address: FFF52H (IICF0), FFF56H (IICF1) After reset: 00H Symbol <7> <6> <1> <0> IICFn STCFn IICBSYn STCENn IICRSVn STCFn STTn clear flag...
Page 461: Iica Control Register N1 (Iicctln1)
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.3.5 IICA control register n1 (IICCTLn1) This register is used to set the operation mode of I C and detect the statuses of the SCLAn and SDAAn pins. The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn bits are read-only.
Page 462 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 15 Format of IICA control register n1 (IICCTLn1) (2/2) CLDn Detection of SCLAn pin level (valid only when IICEn = 1) The SCLAn pin was detected at low level. The SCLAn pin was detected at high level.
Page 463: Iica Low-Level Width Setting Register N (Iicwln)
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.3.6 IICA low-level width setting register n (IICWLn) This register is used to set the low-level width (t ) of the SCLAn pin signal that is output by serial interface IICA and to control the SDAAn pin signal.
Page 464: Register To Control Port Function Of Serial I/O Pin
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.3.8 Register to control port function of serial I/O pin When serial interface IICA is used, set the registers (port mode register 6 (PM6) and port register 6 (P6)) that controls the port functions for alternately used with SCLAn pin and SDAAn pin.
Page 465: I 2 C Bus Mode Functions
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.4 C Bus Mode Functions 15.4.1 Pin configuration The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows. (1) SCLAn..This pin is used for serial clock input and output.
Page 466: Setting Transfer Clock By Using Iicwln And Iicwhn Registers
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.4.2 Setting transfer clock by using IICWLn and IICWHn registers (1) Setting transfer clock on master side Transfer clock = IICWL + IICWH + f At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
Page 467 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Remark 1. Calculate the rise time (t ) and fall time (t ) of the SDAAn and SCLAn signals separately, because they differ depending on the pull-up resistance and wire load. Remark 2. IICWLn: IICA low-level width setting register n...
Page 468: I 2 C Bus Definitions And Control Methods
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5 C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 15 - 19 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the C bus’s serial data bus.
Page 469: Addresses
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 470: Acknowledge (Ack)
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.4Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
Page 471: Stop Condition
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.5 Stop condition When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.
Page 472: Wait
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLAn pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
Page 473 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 26 Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKEn = 1) Master and slave both wait Master after output of ninth clock...
Page 474: Canceling Wait
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.7 Canceling wait The I C usually cancels a wait state by the following processing. • Writing data to the IICA shift register n (IICAn) • Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) Note •...
Page 475: Interrupt Request (Intiican) Generation Timing And Wait Control
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.8 Interrupt request (INTIICAn) generation timing and wait control The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is generated and the corresponding wait control, as shown in Table 15 - 2.
Page 476: Address Match Detection Method
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (4) Wait cancellation method The four wait cancellation methods are as follows. • Writing data to the IICA shift register n (IICAn) • Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) Note •...
Page 477: 15.5.11 Extension Code
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.11 Extension code (1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXCn) is set to 1 for extension code reception and an interrupt request (INTIICAn) is issued at the falling edge of the eighth clock.
Page 478: 15.5.12 Arbitration
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STTn bit is set to 1 before the STDn bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 479 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Table 15 - 4 Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing During address transmission At falling edge of eighth or ninth clock following byte Note 1...
Page 480: 15.5.13 Wakeup Function
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIICAn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICAn signal from occurring when addresses do not match.
Page 481 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 29 Flow When Setting WUPn = 0 upon Address Match (Including Extension Code Reception) STOP mode state INTIICAn = 1? WUPn = 0 Wait Wait for 5 f clocks. Reading IICSn Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA .
Page 482 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 30 When Operating as Master Device after Releasing STOP Mode other than by INTIICAn START SPIEn = 1 WUPn = 1 Wait for 3 f clocks. Wait STOP instruction STOP mode state...
Page 483: Communication Reservation
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.14Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
Page 484 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 31 shows the Communication Reservation Timing. Figure 15 - 31 Communication Reservation Timing Write to Program processing STTn = 1 IICAn Set SPDn Hardware processing Communication reservation STDn INTIICAn SCLAn SDAAn...
Page 485 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 33 shows the Communication Reservation Protocol. Figure 15 - 33 Communication Reservation Protocol SET1 STTn Sets STTn flag (communication reservation) Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM )
Page 486 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1) When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 487: 15.5.15 Cautions
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.15 Cautions (1) When STCENn = 0 Immediately after I C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 488: 15.5.16 Communication Operations
The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the RL78/G1H as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
Page 489 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (1) Master operation in single master system Figure 15 - 34 Master Operation in Single-Master System START Setting the PER0 register Release the serial interface IICA from the reset status and start clock supply.
Page 490 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (2) Master operation in multimaster system Figure 15 - 35 Master Operation in Multi-Master System (1/3) START Setting the PER0 register Release the serial interface IICA from the reset status and start clock supply.
Page 491 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 36 Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STTn = 1 (generates a start condition). Note Secure wait time by software. Wait MSTSn = 1?
Page 492 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 37 Master Operation in Multi-Master System (3/3) Starts communication Writing IICAn (specifies an address and transfer direction). INTIICAn interrupt occurs? Waits for detection of ACK. MSTSn = 1? ACKDn = 1?
Page 493 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
Page 494 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
Page 495 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following operations are performed.
Page 496: Timing Of I C Interrupt Request (Intiican) Occurrence
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.5.17 Timing of I C interrupt request (INTIICAn) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn, and the value of the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Page 497 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (1) Master device operation Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 1000×110B...
Page 498 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIMn = 0 STTn = 1 SPTn = 1 ↓ ↓ AD6 to AD0 R/W ACK D7 to D0...
Page 499 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 1010×110B ▲2: IICSn = 1010×000B...
Page 500 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIMn = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0001×110B ▲2: IICSn = 0001×000B...
Page 501 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches with SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0...
Page 502 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0...
Page 503 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0...
Page 504 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIMn = 0...
Page 505 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 R/W ACK D7 to D0 ▲1: IICSn = 0010×010B...
Page 506 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0...
Page 507 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0...
Page 508 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (4) Operation without communication Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 00000001B Remark : Generated only when SPIEn = 1...
Page 509 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0101×110B ▲2: IICSn = 0001×100B ▲3: IICSn = 0001××00B 4: IICSn = 00000001B Remark ▲: Always generated : Generated only when SPIEn = 1 ×...
Page 510 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0110×010B ▲2: IICSn = 0010×110B ▲3: IICSn = 0010×100B ▲4: IICSn = 0010××00B 5: IICSn = 00000001B Remark ▲: Always generated...
Page 511 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0110×010B Sets LRELn = 1 by software 2: IICSn = 00000001B Remark ▲: Always generated...
Page 512 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 10001110B ▲2: IICSn = 01000100B 3: IICSn = 00000001B Remark ▲: Always generated : Generated only when SPIEn = 1...
Page 513 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA (ii) Extension code AD6 to AD0 R/W ACK D7 to Dm AD6 to AD0 R/W ACK D7 to D0 ▲1: IICSn = 1000×110B ▲2: IICSn = 01100010B Sets LRELn = 1 by software 3: IICSn = 00000001B Remark ▲: Always generated...
Page 514 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 ▲1: IICSn = 1000×110B...
Page 515 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 ▲1: IICSn = 1000×110B ▲2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Page 516 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 ▲1: IICSn = 1000×110B...
Page 517: Timing Charts
RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA 15.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 518 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 40 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICAn <5>...
Page 519 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 15 - 40 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 520 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 41 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4) (2) Address ~ data ~ data Master side Note 1...
Page 521 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 15 - 41 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 522 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 42 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4) (3) Data ~ data ~ stop condition Master side Note 1 IICAn <9>...
Page 523 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 15 - 42 are explained below. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device.
Page 524 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 43 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4) (4) Data ~ restart condition ~ address Master side IICAn <iii>...
Page 525 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The following describes the operations in Figure 15 - 43 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the processing to step <iii>, the data transmission step.
Page 526 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 44 Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICAn <2>...
Page 527 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 15 - 44 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 528 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 45 Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Address ~ data ~ data Master side IICAn ACKDn...
Page 529 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 15 - 45 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 530 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA Figure 15 - 46 Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition Master side...
Page 531 RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 15 - 46 are explained below. <8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICAn: end of transfer).
Page 532: Data Transfer Controller (Dtc)
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) The higher 8 bits for the address described in this chapter are the bits 15 to 8 of 20-bit address shown below. 20-bit address Highest 4 bits...
Page 533 RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) Table 16 - 1 DTC Specifications Item Specification Interrupt request Normal mode When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed, the activation source interrupt request is generated for the CPU, and interrupt handling is performed on completion of the data transfer.
Page 534: Configuration Of Dtc
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.2 Configuration of DTC Figure 16 - 1 shows the DTC Block Diagram. Figure 16 - 1 DTC Block Diagram Peripheral interrupt signal Interrupt source/ Data transfer control transfer activation source selection Peripheral interrupt signal...
Page 535: Registers Controlling Dtc
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3 Registers Controlling DTC Table 16 - 2 lists the Registers Controlling DTC. Table 16 - 2 Registers Controlling DTC Register Name Symbol Peripheral enable register 1 PER1 DTC activation enable register 0...
Page 536: Allocation Of Dtc Control Data Area And Dtc Vector Table Area
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.1 Allocation of DTC Control Data Area and DTC Vector Table Area The DTCBAR register is used to set the 256-byte area where DTC control data and the vector table within the RAM area.
Page 537: Control Data Allocation
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.2 Control Data Allocation Control data is allocated beginning with each start address in the order: Registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj (j = 0 to 23). The higher 8 bits for start addresses 0 to 23 are set by the DTCBAR register, and the lower 8 bits are separately set according to the vector table assigned to each activation source.
Page 538: Vector Table
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.3 Vector Table When the DTC is activated, one control data is selected according to the data read from the vector table which has been assigned to each activation source, and the selected control data is read from the DTC control data area.
Page 539 RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) Table 16 - 5 DTC Activation Sources and Vector Addresses Source DTC Activation Sources (Interrupt Request Source) Vector Address Priority Reserved Address set in DTCBAR register +00H Highest INTP0 Address set in DTCBAR register +01H...
Page 540: Peripheral Enable Register 1 (Per1)
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.4 Peripheral enable register 1 (PER1) The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
Page 541: Dtc Control Register J (Dtccrj) (J = 0 To 23)
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.5 DTC control register j (DTCCRj) (j = 0 to 23) The DTCCRj register is used to control the DTC operating mode. Figure 16 - 6 Format of DTC control register j (DTCCRj) Address: Refer to 16.3.2 Control Data Allocation .
Page 542: Dtc Block Size Register J (Dtblsj) (J = 0 To 23)
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.6 DTC block size register j (DTBLSj) (j = 0 to 23) This register is used to set the block size of the data to be transferred by one activation. Figure 16 - 7 Format of DTC block size register j (DTBLSj) Address: Refer to 16.3.2 Control Data Allocation .
Page 543: Dtc Transfer Count Reload Register J (Dtrldj) (J = 0 To 23)
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23) This register is used to set the initial value of the transfer count register in repeat mode. Since the value of this register is reloaded to the DTCCT register in repeat mode, set the same value as the initial value of the DTCCT register.
Page 544: Dtc Activation Enable Register I (Dtceni) (I = 0 To 4)
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4) This is an 8-bit register which enables or disables DTC activation by interrupt sources. Table 16 - 6 lists the Correspondences between Interrupt Sources and Bits DTCENi0 to DTCENi7.
Page 545 RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) DTCENi2 DTC activation enable i2 Activation disabled Activation enabled The DTCENi2 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt. DTCENi1 DTC activation enable i1 Activation disabled Activation enabled The DTCENi1 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
Page 546 RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) Table 16 - 6 Correspondences between Interrupt Sources and Bits DTCENi0 to DTCENi7 Register DTCENi7 Bit DTCENi6 Bit DTCENi5 Bit DTCENi4 Bit DTCENi3 Bit DTCENi2 Bit DTCENi1 Bit DTCENi0 Bit DTCEN0 Reserved INTP0...
Page 547: Dtc Base Address Register (Dtcbar)
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.3.12 DTC base address register (DTCBAR) This is an 8-bit register used to set the following addresses: the vector address where the start address of the DTC control data area is stored and the address of the DTC control data area. The value of the DTCBAR register is handled as the higher 8 bits to generate a 16-bit address.
Page 548: Activation Sources
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.4.1 Activation Sources The DTC is activated by an interrupt signal from the peripheral functions. The interrupt signals to activate the DTC are selected with the DTCENi (i = 0 to 4) register.
Page 549: Normal Mode
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.4.2 Normal Mode One to 256 bytes of data are transferred by one activation during 8-bit transfer and 2 to 512 bytes during 16-bit transfer. The number of transfers can be 1 to 256 times. When the data transfer causing the DTCCTj (j = 0 to 23)
Page 550: Repeat Mode
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.4.3 Repeat Mode One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be specified as the repeat area. The number of transfers can be 1 to 255 times. On completion of the specified number of transfers, the DTCCTj (i = 0 to 23) register and the address specified for the repeat area are initialized to continue transfers.
Page 551 RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) Figure 16 - 16 Data Transfers in Repeat Mode DTCCTj register ≠ 1 FFFFFH Transfer Size of the data block to be transferred by one activation (N bytes) DTBLSj register = N DTCCTj register...
Page 552: Chain Transfers
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.4.4 Chain Transfers When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), multiple data transfers can be continuously performed by one activation source. When the DTC is activated, one control data is selected according to the data read from the vector address corresponding to the activation source, and the selected control data is read from the DTC control data area.
Page 553: Cautions For Dtc
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.5 Cautions for DTC 16.5.1 Setting DTC Control Data and Vector Table • Do not access the DTC extended special function register (2nd SFR), the DTC control data area, the DTC vector table area, or the general-register (FFEE0H to FFEFFH) space using a DTC transfer.
Page 554: Dtc Pending Instruction
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.5.3 DTC Pending Instruction Even if a DTC transfer request is generated, DTC transfer is held pending immediately after the following instructions. Also, the DTC is not activated between PREFIX instruction code and the instruction immediately after that code.
Page 555: Number Of Dtc Execution Clock Cycles
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.5.5 Number of DTC Execution Clock Cycles Table 16 - 9 lists the Operations Following DTC Activation and Required Number of Cycles for each operation. Table 16 - 9 Operations Following DTC Activation and Required Number of Cycles...
Page 556: Dtc Response Time
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.5.6 DTC Response Time Table 16 - 12 lists the DTC Response Time. The DTC response time is the time from when the DTC activation source is detected until DTC transfer starts. It does not include the number of DTC execution clocks.
Page 557: Operation In Standby Mode Status
RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC) 16.5.8 Operation in Standby Mode Status Status DTC Operation HALT mode Operable (Operation is disabled while in the low power consumption RTC mode) STOP mode Note 2 DTC activation sources can be accepted...
Page 558: Event Link Controller (Elc)
RL78/G1H CHAPTER 17 EVENT LINK CONTROLLER (ELC) CHAPTER 17 EVENT LINK CONTROLLER (ELC) 17.1 Functions of ELC The event link controller (ELC) mutually connects (links) events output from each peripheral function. By linking events, it becomes possible to coordinate operation between peripheral functions directly without going through the CPU.
Page 559: Registers Controlling Elc
RL78/G1H CHAPTER 17 EVENT LINK CONTROLLER (ELC) 17.3 Registers Controlling ELC 17.3.1 Event output destination select register n (ELSELRn) (n = 00, 03, 04, 07, 13, 16 to 23) An ELSELRn register links each event signal to an operation of an event-receiving peripheral function (link destination peripheral function) after reception.
Page 560 RL78/G1H CHAPTER 17 EVENT LINK CONTROLLER (ELC) Table 17 - 1 Correspondence Between ELSELRn Registers (n = 00 to 25) and Peripheral Functions Register Name Event Generator (Output Origin of Event Input n) Event Description ELSELR00 External interrupt edge detection 0...
Page 561: Elc Operation
RL78/G1H CHAPTER 17 EVENT LINK CONTROLLER (ELC) 17.4 ELC Operation The path for using an event signal generated by a peripheral function as an interrupt request to the interrupt control circuit is independent from the path for using it as an ELC event. Therefore, each event signal can be used as an event signal for operation of an event-receiving peripheral function, regardless of interrupt control.
Page 562: Rf Transceiver
RL78/G1H CHAPTER 18 RF TRANSCEIVER CHAPTER 18 RF TRANSCEIVER Precautions for use of RF transceiver The international standard and the domestic laws and regulations restrict use of the wireless receiver and transmitter. Be sure to observe the standard, laws, regulations of the country where they are used.
Page 563: Rf Transceiver Overview
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.1 RF Transceiver Overview RF transceiver supports 2FSK/GFSK and 4FSK/GFSK modulations with lower power consumption, and corresponds to the operation within the frequency band between 863 MHz and 928 MHz. This transceiver is best suited to the applications used for smart meter (electricity, gas, tap water) supporting products, HEMS controller, wireless sensor network, and others.
Page 564: Pin Functions
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.2 Pin Functions 18.2.1 Digital pin This indicates the digital pin of RF unit (RF transceiver). (1) STANDBY This is an enable input pin for control of RF unit. Setting to High enables control of RF unit, and Low disables it and turns the power supply to the RF internal circuit off.
Page 565: Analog Pin
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.2.2 Analog pin The analog pins of the RF transceiver are described below. (1) RFIP This is an input pin (RF reception) of the RF transceiver. (2) RFOUT This is an output pin (RF transmission) of the RF transceiver.
Page 566: Configuration Of Rf Transceiver
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.3 Configuration of RF Transceiver RF transceiver consists of the analog block, digital block, power supply circuit block, oscillator block, and interface block.Figure 18 - 1 shows the block diagram. The next section provides description in detail.
Page 567: Analog Block
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.3.2 Analog block The analog block consists of RF transmission/reception circuits. Figure 18 - 2 shows the block diagram of the RF transmission/reception block. Figure 18 - 2 RF Transmission/Reception Block Analog block Filter block...
Page 568: Oscillator Block
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.3.3 Oscillator block The oscillator block generates the reference clock to be supplied to the internal circuit of RF unit. This block also has the function to externally output the generated reference clock. RF reference clock and RF clock output are classified into the following types.
Page 569: Baseband Function
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.4 Baseband Function 18.4.1 Configuration Figure 18 - 3 shows the baseband block diagram. Figure 18 - 3 Baseband Block Diagram Demodulation RF receive control block Receive RAM Serial control interface Frame control storage Cipher...
Page 570: Frame Configuration
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.4.2 Frame configuration (1) RF transmission mode Automatically generates and outputs the transmission frame. Figure 18 - 4 shows the transmission frame configuration. The frame configurations after the PHR other than those of the mode switch frame and the mode switch frame change.
Page 571: Index
RL78/G1H CHAPTER 18 RF TRANSCEIVER (2) Preamble value and SFD value Set preamble length values to preamble length setting register (00A7H, 00A6H addresses) equal or more than the below. Table 18 - 2 For Normal Receive Condition Preamble length Symbol rate (ksps) Modification index <R>...
Page 572 RL78/G1H CHAPTER 18 RF TRANSCEIVER (3) Configuration of PHR <1> In the case other than the Mode Switch frame Figure 18 - 5 shows the PHR bit configuration in the case other than the Mode Switch frame. The respective PHR bits automatically capture the set value and transmit it to the corresponding register.
Page 573 RL78/G1H CHAPTER 18 RF TRANSCEIVER <2>In the case of the Mode Switch frame Figure 18 - 6 shows the PHR bit configuration in the case of the Mode Switch frame. The respective PHR bits automatically capture the set value and transmit it to the corresponding register.
Page 574: Baseband Interrupt
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.4.3 Baseband Interrupt Table 18 - 4 shows the interrupt sources. If one or more bits are “1” in interrupt source bits in the table enabled by baseband interrupt registers 0 to 2, INTOUT pin outputs high level. If the all interrupt source bits are “0”, the pin outputs low level.
Page 575: Baseband Function Controlling Register
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.4.4 Baseband Function Controlling Register Table 18 - 5 and Table 18 - 6 show the registers to control the baseband function. For how to access the control register, see 18.5. Table 18 - 5 Baseband Function Controlling Register (1/2)
Page 576 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 6 Baseband Function Controlling Register (2/2) Register name Symbol Address Reset value (40) CSMA-CA start count register CSMASTACOUNT 004FH, 004EH 000EH (41) Communication status register 1 COMSTATE1 0066H (42) Communication status register 2...
Page 577 RL78/G1H CHAPTER 18 RF TRANSCEIVER (1) RF start register (BBRFCON) Enables the RF function by setting 1 to the RF function enable bit. Releases the analog circuit reset by setting 1 to the analog reset release bit. The BBRFCON register consists of 8 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 578 RL78/G1H CHAPTER 18 RF TRANSCEIVER (2) Transmit/receive reset register (BBTXRXRST) This register stops the RF communication. Processes of reception, during the CCA and calibration can be stopped by setting 1 to the RF communication stop bit. (It enters into the IDLE state after the stop) In addition, the processes of automatic ACK reply, the automatic receive switch mode function, and others are also canceled.
Page 579 RL78/G1H CHAPTER 18 RF TRANSCEIVER (3) Transmit/receive mode register 0 (BBTXRXMODE0) This register sets the various types of the RF transmit/receive mode. Set 1 to the CCA type bit when performing the CCA or ED. Enables the selection whether to perform the automatic ACK reply action after the completion of receive by using the automatic ACK mode enable bit.
Page 580 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 9 Transmit/Receive Mode Register 0 (BBTXRXMODE0) Format Address: 0002H After reset: 00H Symbol BBTXRX INTRAPANEN BEACON BATLIFEEXT AUTORCV1 AUTORCV0 AUTOACKEN CCATYPE0 MODE0 INTRAPANEN intraPAN enable bit intraPAN disabled intraPAN enabled BEACON BEACON mode bit...
Page 581 RL78/G1H CHAPTER 18 RF TRANSCEIVER (4) Transmit/receive mode register 1 (BBTXRXMODE1) This register sets the various types of the RF transmit/receive mode. The CCA result select bit can be used to select between the CCA/ED value and the RSSI value when reading the RSSI/CCA result register.
Page 582 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 10 Transmit/Receive Mode Register 1 (BBTXRXMODE1) Format Address: 0003H After reset: C0H Symbol BBTXRX ACKRCVPOI SQCNUMSU ACKFV1 ACKFV0 ACKFVEN CCASEL MODE1 ACKRCVPOI ACK receive point setting bit Upon completion of the receive...
Page 583 The values in Table 18 - 52 to Table 18 - 59 Settings Required for Each Data Rate are reference measured on evaluation board of Renesas Electronics. Caution Refer to the latest application note for setting data in Table 18 - 7 when to use the product.
Page 584 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 7 Register setting for loss of input signal level from antenna (1/4) 1dB loss Frequency Data 0044 band Mode rate 0483 047C 047D 047E 047F FEC: FEC: identifier (kbps) Enabled Disable 863MHz...
Page 585 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 7 Register setting for loss of input signal level from antenna (2/4) 2dB loss Frequency Data 0044 band Mode rate 0483 047C 047D 047E 047F FEC: FEC: identifier (kbps) Enabled Disable 863MHz...
Page 586 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 7 Register setting for loss of input signal level from antenna (3/4) 3dB loss Frequency Data 0044 band Mode rate 0483 047C 047D 047E 047F FEC: FEC: identifier (kbps) Enabled Disable 863MHz...
Page 587 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 7 Register setting for loss of input signal level from antenna (4/4) 4dB loss Frequency Data 0044 band Mode rate 0483 047C 047D 047E 047F FEC: FEC: identifier (kbps) Enabled Disable 863MHz...
Page 588 RL78/G1H CHAPTER 18 RF TRANSCEIVER (6) Enhanced-ACK mode register (BBEACKMODE) This register sets the enhanced ACK mode. The BBEACKMODE register consists of 8 bits and can be accessed (serial interface communication) in 8 bit unit. Reset signal generation sets this register to 01H.
Page 589 RL78/G1H CHAPTER 18 RF TRANSCEIVER (7) Transmit/receive status register 0 (BBTXRXST0) This register stores the RF transmit/receive status. It stores the CCA judge result in bit 0. It stores the CRC judge result in bit 1. The CRC result corresponding to the save bank which is specified by the receive data save bank select bit is read out when reading.
Page 590 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 13 Transmit/Receive Status Register 0 (BBTXRXST0) Format Note Address: 0007H After reset: 80H Symbol BBTXRXS RCVRAMST RCVPEND RCVBANK1 RCVBANK0 TRNRCVSQC CSMACA RCVRAMST Receive RAM bank pointer bit Receive RAM bank 0 Receive RAM bank 1...
Page 591 RL78/G1H CHAPTER 18 RF TRANSCEIVER (8) Transmit/receive mode register 2 (BBTXRXMODE2) This register sets the various types of the RF transmit/receive mode. The automatic CRC disable bit can be used to select between to transmit with the CRC calculation result automatically attached upon transmit, and to transmit the data on the RAM.
Page 592 RL78/G1H CHAPTER 18 RF TRANSCEIVER (9) Transmit/receive mode register 3 (BBTXRXMODE3) This register sets the various types of the RF transmit/receive mode. The address filter enable bit can be used to enable the address filter upon receiving. When this bit is set to “1”, address filter on first address side is enabled.
Page 593 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 15 Transmit/Receive Mode Register 3 (BBTXRXMODE3) Format Address: 000AH After reset: 00H Symbol BBTXRX ADFGENMO ADFEXTEN RCVOVERW RCVBANKSEL LVLFILEN RXEN PANCORD ADRSFILEN MODE3 ADFGENMO Address filter general-purpose mode bit The WiSUN mode...
Page 594 RL78/G1H CHAPTER 18 RF TRANSCEIVER (10) Transmit/receive status register 1 (BBTXRXST1) The receive data save bank pointer bit can be used to check the bank which stores the data, for example frame length of the received frame. It indicates 1 after reset or initialization.
Page 595 RL78/G1H CHAPTER 18 RF TRANSCEIVER (11) Transmit/receive control register (BBTXRXCON) This register controls the RF transmit/receive. Setting “1” to the receive trigger bit starts warm-up of the RF circuit and enters into the reception available state after 240 μs. Setting “1” to the transmit trigger bit starts warm-up of the RF circuit and enters transmission after 350 μs.
Page 596 RL78/G1H CHAPTER 18 RF TRANSCEIVER (12) CSMA control register 0 (BBCSMACON0) This register controls the CSMA-CA operation. Setting “1” to the automatic CSMA-CA start bit starts the CSMA-CA operation. Be sure to set this bit under the state it is IDLE. Note that these bits are automatically cleared to “0” upon completion of the CSMA-CA operation.
Page 597 RL78/G1H CHAPTER 18 RF TRANSCEIVER (13) CCA level threshold setting register (BBCCAVTH) This register is used to set the threshold level to judge the CCA. It judges as busy for the CCA value which is the value set to this register or greater.The value is set as 2’s complement. The setting unit is dBm (ex.
Page 598 RL78/G1H CHAPTER 18 RF TRANSCEIVER (14) Transmit/receive status register 2 (BBTXRXST2) This register stores the information on the various types of the RF transmit/receive status. The receive RAM bank flag bit is used to indicate the receive RAM bank upon start of the reception.
Page 599 RL78/G1H CHAPTER 18 RF TRANSCEIVER (15) Transmit/receive mode register 4 (BBTXRXMODE4) This register sets the various types of the RF transmit/receive mode. The CCA interrupt select bit can be used to select the CCA interrupt source between the time upon completion of the CCA sequence and the time upon completion of the CSMA-CS sequence.
Page 600 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 21 Transmit/Receive Mode Register 4 (BBTXRXMODE4) Format Address: 0011H After reset: 01H Symbol BBTXRX TIMEOUTINT TIMEOUTRCV INTOUTSEL CCAINTSEL MODE4 TIMEOUTIN Receive timeout interrupt switch bit TSEL Byte receive interrupt Receive timeout interrupt...
Page 601 RL78/G1H CHAPTER 18 RF TRANSCEIVER (16) CSMA control register 1 (BBCSMACON1) This register controls the CSMA-CA operation. The NB bit is used to set the macMaxCSMABackoff value. (Initial value is 0H) The CW bit is used to set the CW value. (Initial value is 2H) The BBCSMACON1 register consists of 8 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 602 RL78/G1H CHAPTER 18 RF TRANSCEIVER (17) CSMA control register 2 (BBCSMACON2) This register controls the CSMA-CA operation. The BEMAX bit is used to set the macMaxBE value. (Initial value is 5 ) Set the greater value for the BEMAX bit than the BEMIN bit setting value.
Page 603 RL78/G1H CHAPTER 18 RF TRANSCEIVER (18) PAN identifier register 0 (BBPANID0) This register is used to set the PAN identifier of the first address filter. It consists of 16 bits and is used to detect the match with a received PAN identifier.
Page 604 RL78/G1H CHAPTER 18 RF TRANSCEIVER (20) Extended address register 0 (BBEXTENDAD00 to BBEXTENDAD03) These registers are used to set the extended address of the first address filter. They consist of 64 bits (16 bit timed by 4) and are used to detect the match with a received extended address.
Page 605 RL78/G1H CHAPTER 18 RF TRANSCEIVER (21) Timer read registers (BBTIMEREAD0, BBTIMEREAD1) These registers are used to read the current count value of the 32-bit timer. Read from the lower bytes when reading the timer count value. Then continue to read the upper bytes because the count value is latched when reading the 0020 address of LSB.
Page 606 RL78/G1H CHAPTER 18 RF TRANSCEIVER (22) Timer compare registers 0 and 1 (BBTCOMP0REG0 to BBTCOMP2REG0, BBTCOMP0REG1 to BBTCOMP2REG1) These registers are used to compare with the 32-bit timer. Each of them includes three channels to compare each of the channels with the 32-bit timer.
Page 607 RL78/G1H CHAPTER 18 RF TRANSCEIVER (23) Time stamp registers 0 and 1 (BBTSTAMP0, BBTSTAMP1) These registers are used to store the timer values upon the packet data receive start, upon the completion of the packet data reception, or upon completion of the packet data transmission. The respective time stamps of receive/transmit are stored.
Page 608 RL78/G1H CHAPTER 18 RF TRANSCEIVER (24) Timer control register (BBTIMECON) This register is used to control the timer in this transceiver. The timer count enable bit controls the 32-bit timer count operation. Setting “1” enables the timer count. In addition, setting “0” stops the timer while the count value is initialized to 00000000H.
Page 609 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 33 Timer Control Register (BBTIMECON) Format Address: 0034H After reset: 00H Symbol BBTIMEC CNTSRCSEL STAMPRDSE STAMPRDSE COMP0TRGS STAMPTIMS COMP0TRG TIMEEN CNTSRCSE Count source switch bit Prescaler output (1 μs) Data rate STAMPRDS...
Page 610 RL78/G1H CHAPTER 18 RF TRANSCEIVER (25) Back off period register (BBBOFFPROD) This register is used to control the back off period. The back off period auto random enable bit is used to automatically generate the random value with setting the value set to the back off period bit as an initial value, and to set the back off period value in the CSMA- CA circuit.
Page 611 RL78/G1H CHAPTER 18 RF TRANSCEIVER (26) Baseband interrupt source register 0 (BBINTREQ0) This register is used to indicate the baseband interrupt source. This register indicates that “1” is set to the interrupt source corresponding to each interrupt occurrence timing so that there is an interrupt request. When reading this register, only the bit from which 1 is read is cleared to 0.
Page 612 RL78/G1H CHAPTER 18 RF TRANSCEIVER (27) Baseband interrupt source register 1 (BBINTREQ1) This register is used to indicate the baseband interrupt source. A bit of this register indicates that “1” is set to the interrupt source corresponding to each interrupt occurrence timing so that there is an interrupt request.
Page 613 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 36 Baseband Interrupt Source Register 1 (BBINTREQ1) Format <R> Address: 0037H After reset: 00H Symbol BBINTREQ1 LVLFILINTREQ MODESWINTREQ ROVRINTREQ ADRSINTREQ RCVSTINTREQ RCV1INTREQ RCV0INTREQ RCVFININTREQ LVLFILINTREQ Receive level filter interrupt source bit No request...
Page 614 RL78/G1H CHAPTER 18 RF TRANSCEIVER (28) Baseband interrupt source register 2 (BBINTREQ2) This register is used to indicate the baseband interrupt source. This register indicates that “1” is set to the interrupt source corresponding to each interrupt occurrence timing so that there is an interrupt request. When reading this register, only the bit from which 1 is read is cleared to 0.
Page 615 RL78/G1H CHAPTER 18 RF TRANSCEIVER (29) Baseband interrupt enable register 0 (BBINTEN0) This register is used to enable the baseband interrupt. This register enables the interrupt output from the INTOUT pin upon generation of each interrupt. Set “1” to the corresponding interrupt enable bit when you want to enable the interrupt output.
Page 616 RL78/G1H CHAPTER 18 RF TRANSCEIVER (30) Baseband interrupt enable register 1 (BBINTEN1) This register is used to enable the baseband interrupt. This register enables the interrupt output from the INTOUT pin upon generation of each interrupt. Set “1” to the corresponding interrupt enable bit when you want to enable the interrupt output.
Page 617 RL78/G1H CHAPTER 18 RF TRANSCEIVER (31) Baseband interrupt enable register 2 (BBINTEN2) This register is used to enable the baseband interrupt. This register enables the interrupt output from the INTOUT pin upon generation of each interrupt. Set “1” to the corresponding interrupt enable bit when you want to enable the interrupt output.
Page 618 RL78/G1H CHAPTER 18 RF TRANSCEIVER (32) CSMA control register 3 (BBCSMACON3) This register controls the CSMA-CA operation. The BEMIN bit is used to set the macMinBE value. (Initial value is 3H.) Set the smaller value for the BEMIN bit than the BEMAX bit setting value.
Page 619 RL78/G1H CHAPTER 18 RF TRANSCEIVER (33) ACK counter compare registers 0 and 1 (ACKCOMP0, ACKCOMP1) These registers are used to set each of the timings upon automatic ACK reply mode. The ACKCOMP0 and ACKCOMP1 registers consist of 16 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 620 RL78/G1H CHAPTER 18 RF TRANSCEIVER (34) ACK counter initial value register (ACKINI) This register is used to set each of the timings upon automatic ACK reply mode. The ACKINI register consists of 16 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 621 RL78/G1H CHAPTER 18 RF TRANSCEIVER (35) Receive level threshold setting register (BBLVLVTH) This register is used to set the threshold value of the receive level. The value is set as 2's complement The setting unit is dBm (ex. ”19EH” is ”-98dBm”).
Page 622 RL78/G1H CHAPTER 18 RF TRANSCEIVER (36) ACK reply time setting register (ACKRTNTIM) This register is used to set the ACK reply time in the non-BEACON mode. The ACKRTNTIM register consists of 16 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 623 RL78/G1H CHAPTER 18 RF TRANSCEIVER (37) Automatic receive switch compare register (AUTORCVCNT) This register is used to set the time until the TRG_ON signal is set to the high level for the automatic receive switch after the completion of transmit/receive when the mode is set to the automatic receive switch mode.
Page 624 RL78/G1H CHAPTER 18 RF TRANSCEIVER (38) Back off cycle register (BOFFPERIOD) This register is used to set the back off cycle. Initial value: 0071H= 113 symbols (Set value: 1H = 1 symbol) The BOFFPERIOD register consists of 16 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 625 RL78/G1H CHAPTER 18 RF TRANSCEIVER (39) CSMA-CA end count register (CSMAENDCOUNT) This register is used to set the time until the wait status after the completion of CCA when the automatic CSMA-CA sequence is used. Initial value is 0080H = 128 μs. (Set value: 1H =1 μs) The CSMAENDCOUNT register consists of 16 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 626 RL78/G1H CHAPTER 18 RF TRANSCEIVER (40) CSMA-CA start count register (CSMASTACOUNT) This register is used to set the time of warm-up until the start of CCA when the automatic CSMA-CA sequence is used. Set the minimum number of symbols which is greater than 144 μs. Initial value: 000EH =...
Page 627 RL78/G1H CHAPTER 18 RF TRANSCEIVER (41) Communication status register 1 (COMSTATE1) This register is used to confirm each state in communication. Transmitting status bit shows transmit state. CCA status bit shows CCA state. Receiving frame status bit shows frame receive state.
Page 628 RL78/G1H CHAPTER 18 RF TRANSCEIVER (42) Communication status register 2 (COMSTATE2) This register is used to confirm each state in communication. ACK reply status bit shows ACK reply state. Figure 18 - 55 Communication status register 2 (COMSTATE2) Format Address: 0067H...
Page 629 RL78/G1H CHAPTER 18 RF TRANSCEIVER (43) Estimate control register (BBEVAREG) This register is used to set the evaluation mode which is required when obtaining the certification of conformance to technical standards. Setting “1” to both continuous transmission mode and transmit trigger bit enters into the continuous transmission mode.
Page 630 RL78/G1H CHAPTER 18 RF TRANSCEIVER Supplemental explanation 1. Special transmit mode • Preamble part - Transmits the pattern which is set in the preamble setting register. (1 byte or 2 bytes) - Repetitively transmits the number of bytes which is set by the number-of-preamble-byte setting bit.
Page 631 RL78/G1H CHAPTER 18 RF TRANSCEIVER Supplemental explanation 2. Special receive mode • Preamble part - Operates to receive the pattern which is set in the preamble setting register as a preamble pattern. (1 byte or 2 bytes) - The number of bytes which is set by the number-of-preamble-byte setting bit is defined as a repetitive pattern.
Page 632 RL78/G1H CHAPTER 18 RF TRANSCEIVER (44) Back off period register 2 (BBBOFFPROD2) This register is used to set the random value of the back off period when performing the CSMA-CA by using the back off period bits 0 to 7. Set the random value to back off period register 2, and then set “1” to the back off period auto-random enable bit of the back off period register.
Page 633 RL78/G1H CHAPTER 18 RF TRANSCEIVER (45) Communication status register 3 (COMSTATE3) This register is used to display the communication status. The number of retransmissions can be read when the auto-ACK receive mode is enabled by the number-of- retransmission read bit.
Page 634 RL78/G1H CHAPTER 18 RF TRANSCEIVER (46) ACK receive wait time setting register (ACKRCVWIT) This register is used to set the ACK receive wait time after the data transmission. Retransmits data when there is no ACK reply even if it waits for the specified time. Initial value: 0300H = 768 symbols. (Set value:...
Page 635 RL78/G1H CHAPTER 18 RF TRANSCEIVER (47) Retransmission start compare register (RETRNWUP) This register is used to set the time to wait until the power supply is turned on again when performing retransmission. Initial value: 0004H= 4 symbols (Set value: 1H = 1 symbol) The RETRNWUP register consists of 16 bits and can be accessed (serial interface communication) in 8 bit unit.
Page 636 RL78/G1H CHAPTER 18 RF TRANSCEIVER (48) ANTSW output timing setting register (BBANTSWTIMG) This register is used to set the timing for the ANTSW pin output. The time to set the ANTSW pin output to high level can be set after the setting of “1” to the transmission trigger bit.
Page 637 RL78/G1H CHAPTER 18 RF TRANSCEIVER (50) Receive data counter register (BBRXCOUNT) This register is used to indicate the receive data counter value upon reception. It enables the checking of how many bytes of receive data are currently stored to the receive RAM. The value is cleared to “0” when the packet receive ends.
Page 638 RL78/G1H CHAPTER 18 RF TRANSCEIVER (52) Preamble length setting register (BBPAMBL) This register is used to set the preamble length upon transmission. Set value over values shown in Table 18 - 2 and Table 18 - 3. The BBPAMBL register is set by the serial interface in 8-bit units.
Page 639 RL78/G1H CHAPTER 18 RF TRANSCEIVER (54) Symbol rate setting register (BBSYMBLRATE) This register is used to set the symbol rate. This register consists of 24 bits. Table 18 - 8 shows the symbol rate setting examples. The symbol rate is set by using the calculation below.
Page 640 RL78/G1H CHAPTER 18 RF TRANSCEIVER (55) SUBG control register (BBSUBGCON) This register is used to control the SubGHz transceiver. The FEC enable bit for reception is used to enable FEC (CODE) of reception. The FEC mode switch bit is used to switch the FEC encode mode.
Page 641 RL78/G1H CHAPTER 18 RF TRANSCEIVER (56) Modulation method setting register (BBMODSET) This register is used to set the modulation method. The modulation method setting bit is used to set the modulation method. The modulation index setting bit is used to set the modulation index. Table 18 - 9 shows the setting value setting examples for the modulation index setting bit.
Page 642 RL78/G1H CHAPTER 18 RF TRANSCEIVER (57) CCA time register (CCATIME) This register is used to set the time taken for the CCA processing. Initial value: 000DH = 13 symbols (Set value: 1H = 1 symbol). Setting value is up to 2000 symbols.
Page 643 RL78/G1H CHAPTER 18 RF TRANSCEIVER (58) Antenna diversity mode register (BBANTDIV) This register is used to set the antenna diversity mode. The antenna diversity enable bit is used to enable the antenna diversity mode. Enabling this bit switches the GPIO1 pin and the GPIO2 pin to the ANTSELOUT0 pin and the ANTSELOUT1 pin.
Page 644 RL78/G1H CHAPTER 18 RF TRANSCEIVER (59) Mode switch frame transmit register (BBTXMODESW) This register is used to transmit the mode switch frame. The MODESW bit enables the transmission of the mode switch frame. Setting transmission trigger to 1 by setting 1 to this bit transmits the mode switch frame.
Page 645 RL78/G1H CHAPTER 18 RF TRANSCEIVER (61) Transmit data counter register (BBTXCOUNT) This register is used to indicate the transmit data counter value upon transmission. It enables the checking of how many bytes of transmit data are currently transferred to transmitter from the transmit RAM. The value is cleared to “0”...
Page 646 RL78/G1H CHAPTER 18 RF TRANSCEIVER (62) PHY header receive register (BBPHRRX) This register is used to store the PHY header receive data. The values of bits 0 to 2, FCSTYPE, and Data Whitening of the PHY header data when receiving the non- mode switch frame are stored.
Page 647 RL78/G1H CHAPTER 18 RF TRANSCEIVER (63) Preamble setting register (BBPABL) This register is used to optionally set the preamble value. This register consists of 16 bits. Set following values for each modification. 2FSK/2GFSK: 00AAH 4FSK/4GFSK: 00EEH BBPABL register is read via serial interface in 8-bit units.
Page 648 RL78/G1H CHAPTER 18 RF TRANSCEIVER (65) SHR control register (BBSHRCON) This register is used to set the number of bytes in the preamble setting register to be used for the repetitive pattern for preamble by using the number-of-preamble setting bit.
Page 649 RL78/G1H CHAPTER 18 RF TRANSCEIVER (66) ANT0 read register (BBANT0RD) This register is used to store the RSSI value when the ANTSELOUT0 pin output is at the high level. The reading value is corresponding save bank specified by receive data save bank select bit.
Page 650 RL78/G1H CHAPTER 18 RF TRANSCEIVER (68) Antenna switch time register (BBANTDIVTIM) This register is used to set the time to switch between high level and low level outputs of the ANTSELOUT0 and ANTSELOUT1 pin outputs when the antenna diversity is enabled. Initial value: 000AH = 10 symbols (Set value: 1H = 1 symbol).
Page 651 RL78/G1H CHAPTER 18 RF TRANSCEIVER (70) Number-of-receive-byte interrupt compare register (BBRCVINTCOMP) This register is used to generate interrupt depending on the number of received bytes. Generates the interrupt request when receiving the specified number of bytes. The BBRCVINTCOMP register is set via serial interface in 8-bit units.
Page 652 RL78/G1H CHAPTER 18 RF TRANSCEIVER (72) CCA total number register (BBCCATOTAL) This register is used to indicate the total number of count vales upon CSMA-CA. The maximum value of the count is FFH. BBCCATOTAL register is set via serial interface in 8-bit units.
Page 653 RL78/G1H CHAPTER 18 RF TRANSCEIVER (73) RF initial setting register 00 to 02 (RFINI00 to RFINI02) Data read/write area with sub-address is implemented in RF block. These registers are used to set the area. These registers consist of 24 bits.
Page 654 RL78/G1H CHAPTER 18 RF TRANSCEIVER (74) RF initial setting register 10 to 12 (RFINI10 to RFINI12) Data read/write area with sub-address is implemented in RF block. These registers are used to set the area. These registers consist of 24 bits.
Page 655 RL78/G1H CHAPTER 18 RF TRANSCEIVER (75) PAN identifier register 1 (BBPANID1) This register is used to set the PAN identifier of second address filter. It consists of 16 bits and is used to detect the match with a received PAN identifier.
Page 656 RL78/G1H CHAPTER 18 RF TRANSCEIVER (77) Extended address register 1 (BBEXTENDAD10 to BBEXTENDAD13) This register is used to set the extended address of second address filter. It consists of 64 bits (16 bit timed by 4) and is used to detect the match with a received extended address.
Page 657 RL78/G1H CHAPTER 18 RF TRANSCEIVER (78) Receive timeout register (BBTIMEOUT) This register is used to set the timeout time when the automatic reception with timeout mode is enabled. This register consists of 12 bits. BBTIMEOUT register is set via serial interface in 8-bit units.
Page 658 RL78/G1H CHAPTER 18 RF TRANSCEIVER (79) ANTSW control register (ANTSWCON) This register controls the ANTSW signal. The ANTSW signal can be output from the GPIO4 pin by using the ANTSW output enable bit. ANTSWCON register is set via serial interface in 8-bit units.
Page 659 RL78/G1H CHAPTER 18 RF TRANSCEIVER (80) Clock output control register (CLKOUTCON) This register controls the clock output. The clock can be output from the GPIO0 pin by using the clock output enable bit. The output clock can be selected between the clock output select bit 0 and the clock output select bit 1.
Page 660 RL78/G1H CHAPTER 18 RF TRANSCEIVER (81) Port direction register (GPIODIR) This register is used to set the I/O of the respective ports of GPIO. GPIODIR register is set via serial interface in 8-bit units. Reset signal generation clears this register to 00H.
Page 661 RL78/G1H CHAPTER 18 RF TRANSCEIVER (82) Port data register (GPIODATA) This register is used to set the output value when the respective ports of GPIO are set to output. When a GPIO port is set to input, the pin state (H/L) can be read.
Page 662 RL78/G1H CHAPTER 18 RF TRANSCEIVER (83) SFD setting register 2 (BBSFD2) This register is used to set the SFD value for FEC enabled frame transmission/reception when MRFSKSFD bit is 0. Set the following values for each modulation. 2FSK/2GFSK: 000072F6H 4FSK/4GFSK: BFAEFFBEH The BBSFD2 register consists of 32 bits.
Page 663 RL78/G1H CHAPTER 18 RF TRANSCEIVER (84) SFD setting register 3 (BBSFD3) This register is used to set the SFD value for FEC disabled frame transmission/reception when MRFSKSFD bit is 1. Set the following values for each modulation. 2FSK/2GFSK: 0000705EH 4FSK/4GFSK: BFAABBFEH The BBSFD3 register consists of 32 bits.
Page 664 RL78/G1H CHAPTER 18 RF TRANSCEIVER (86) FEC control register (BBFECCON) FEC automatic identification enable bit is used to receive with identification of enabled or disabled FEC. FEC enable bit for transmission is used to set FEC enable or disable of transmission.
Page 665 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 99 FEC Control Register (BBFECCON) Format Address: 010CH After reset: 00H Symbol BBFECCON FECEN FECCON FECEN FECCON MRFSKSFD FECENTX ACKRCV ACKRCV ACKRTN ACKRTN AUTOEN MRFSKSFD MRFSKSFD select bit phyMRFSKSFD = 0 phyMRFSKSFD = 1...
Page 666 RL78/G1H CHAPTER 18 RF TRANSCEIVER (87) Address filter extension address control register (BBADFCON) PAN coordinator 2 bit is used to set whether PAN coordinator on second address filter side. Frame pending 2 bit is used to set enable or disable of frame pending for ACK reply on second address filter side.
Page 667 RL78/G1H CHAPTER 18 RF TRANSCEIVER (88) Antenna diversity mode register 2 (BBANTDIV2) ACK reply antenna switch setting bit is used to select ACK reply antenna for automatic ACK reply. This bit is enabled when ANT receive ANTSW setting disable bit is 0.
Page 668 RL78/G1H CHAPTER 18 RF TRANSCEIVER (89) Lower limit threshold setting register after SFD detection (PWRLOWTH2) <R> This register is used to set threshold for detection of no communication state after SFD detection. This register is valid when receive level filter enable bit is 1.
Page 669: Serial Interface Only For Internal Communication
The serial connection on the user board, etc. is not required since this serial interface is internally connected in RL78/G1H device. Figure 18 - 103 shows the internal serial interface. Figure 18 - 103 Serial Interface Only for Internal Communication...
Page 670: Communication Specification
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.5.2 Communication specification Table 18 - 10 shows the internal communication specification. Table 18 - 10 Internal Communication Specification RF Unit Item CSI20 Target channel Serial array unit (SAU1) channel 0 (CSI20) Serial interface (SPI) Internal pin to be used •...
Page 671: Communication Format
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.5.3 Communication Format Data communication is performed in the communication format of 8-bit unit serial communication. The basic communication format consists of 2 bytes of address and R/W control and 1 byte of data, 3 bytes in total. When the SEN internal pin remains at the low level after reaching 3 bytes of the basic communication, the data cycle occurs in the 4th byte or later.
Page 672 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 11 Contents of Communication Format Format Contents A12 to A0 13-bit address at the access destination. Bit 7 to Bit 3 in the 1st byte and 2nd byte. 2-bit R/W control. Bit 2 and Bit 1 in the 2nd byte.
Page 673: Rf Mode
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.6 RF Mode 18.6.1 RF operating mode RF operating mode is classified into the following three modes. (1) RF transmission mode Indicates the transmission state. Outputs the data written in the data RAM to the RFOUT pin in the specified format.
Page 674: State Transition
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.6.3 State transition Figure 18 - 105 shows the state transition. The state transition to each state of SLEEP, IDLE, TX, and RX is performed according to the setting. The state returns to IDLE automatically after transmit completion, receive completion or CCA completion.
Page 675: Mode Transition
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.6.4 Mode transition (1) Wake Up (transition from SLEEP to IDLE) operation Wake Up operation means the startup sequence operation (transition) of RF unit. Figure 18 - 106 shows the Wake Up operation (RF unit startup sequence) for the XTAL_RF oscillator. While the power is applied externally, set to the high level of STANDBY pin →...
Page 676 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 106 Wake Up Operation (for XTAL_RF Oscillator) <1> <2> <3> State 500 s 50 s 450 s SLEEP IDLE STANDBY OSCDRVSEL RFRESETB SCLK Figure 18 - 107 Wake Up Operation (for REFCLKIN_RF External Clock) <3>...
Page 677 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 13 Description of Each State of Wake Up Operation State Description <1> Time taken from startup of the XTAL_RF oscillator circuit to the oscillation development. When the OSCDRVSEL internal pin is at the low level, the buffer size (current) of the oscillator circuit becomes larger.
Page 678 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 14 Initial Setting Registers Register address (H) Setting value (H) 000A 003A 0048 0052 0053 0054 0057 0058 005A 005C 0078 007C 007E 0086 008E 0092 0094 0096 00A6 0402 0430 043A...
Page 679 RL78/G1H CHAPTER 18 RF TRANSCEIVER (2) Power Down (transition from IDLE to SLEEP) operation Power Down operation stops the internal circuit of RF unit and transits to the low power consumption mode. Set the STANDBY pin to the low level to enter the SLEEP state. When using the XTAL_RF oscillator circuit, set the STANDBY pin to the low level, and then set the OSCDRVSEL internal pin, DON internal pin, and RFRESETB internal pin to the low level respectively.
Page 680: Pin State In Each Rf Mode
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.6.5 Pin state in each RF mode Table 18 - 15 shows the pin states in each RF mode. Table 18 - 15 Function State in Each RF Mode SLEEP IDLE RF Transmission RF Reception...
Page 681: Example Of Procedure For Setting
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.7 Example of Procedure for Setting 18.7.1 Example of procedure for each operation (1) Example of procedure for RF transmission <1> Set to the IDLE state. <2> Set the transmission frequency in the frequency setting register (BBFREQ).
Page 682 RL78/G1H CHAPTER 18 RF TRANSCEIVER (2) Example of procedure for RF reception <1> Set to the IDLE state. <2> Set the reception frequency in the frequency setting register (BBFREQ). For details, see 18.7.2 (3) RF frequency setting for reception. <3> Set the AUTOACKEN bit, AUTORCV0 bit, and BEACON bit of the transmission/reception mode register 0 (BBTXRXMODE0) to ”1”...
Page 683 RL78/G1H CHAPTER 18 RF TRANSCEIVER (3) Example of procedure for CCA <1> Set to the IDLE state. <2> Set the reception frequency in the frequency setting register (BBFREQ). For details, see 18.7.2 (3) RF frequency setting for reception. <3> Set the CCATRG bit of the transmission/reception control register (BBTXRXCON) to ”1” (CCA start).
Page 684: Example Of Procedure For Function Setting
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.7.2 Example of procedure for function setting (1) Example of procedure for RF transmission output power setting <1> See tables according to ”Frequency band identifier” in IEEE802.15.4g frequency/data rate 31.7.7 IEEE802.15.4g frequency/data rate table. When it is 9, Table 18 - 17 to Table 18 - 19. When it is 4, see Table 18 - 20 to Table 18 - 22. When it is 5 to 7, see Table 18 - 23 to Table 18 - 25.
Page 685 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 17 Gain Set (Frequency band identifier = 9) (1/3) 0090H 0092H 00DCH address Bit [4:0] 00DCH address Bit [4:0] 00DCH address Bit [7:4] Gain set address address (00DDH address is set to...
Page 686 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 18 Gain Set (Frequency band identifier = 9) (2/3) 0090H 0092H 00DCH address Bit [4:0] 00DCH address Bit [4:0] 00DCH address Bit [7:4] Gain set address address (00DDH address is set to...
Page 687 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 19 Gain Set (Frequency band identifier = 9) (3/3) 0090H 0092H 00DCH address Bit [4:0] 00DCH address Bit [4:0] 00DCH address Bit [7:4] Gain set address address (00DDH address is set to...
Page 688 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 20 Gain Set (Frequency band identifier = 4) (1/3) 0090H 0092H 00DCH address Bit [4:0] 00DCH address Bit [4:0] 00DCH address Bit [7:4] Gain set address address (00DDH address is set to...
Page 689 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 21 Gain Set (Frequency band identifier = 4) (2/3) 0090H 0092H 00DCH address Bit [4:0] 00DCH address Bit [4:0] 00DCH address Bit [7:4] Gain set address address (00DDH address is set to...
Page 690 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 22 Gain Set (Frequency band identifier = 4) (3/3) 0090H 0092H 00DCH address Bit [4:0] 00DCH address Bit [4:0] 00DCH address Bit [7:4] Gain set address address (00DDH address is set to...
Page 691 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 109 Relationship between Transmission Output Power and Gain Set Output power characteristic 0 10 20 30 40 50 60 70 80 90 100 110 Gain Set R01UH0575EJ0120 Rev. 1.20 Page 673 of 920...
Page 692 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 23 Gain Set (Frequency band identifier = 5 to 7) (1/3) 0090H 0092H 00DCH address Bit [7:4] 00DCH address Bit [4:0] 00DCH address Bit [4:0] Gain set address address (00DDH address is set to...
Page 693 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 24 Gain Set (Frequency band identifier = 5 to 7) (2/3) 0090H 0092H 00DCH address Bit [7:4] 00DCH address Bit [4:0] 00DCH address Bit [4:0] Gain set address address (00DDH address is set to...
Page 694 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 25 Gain Set (Frequency band identifier = 5 to 7) (3/3) 0090H 0092H 00DCH address Bit [7:4] 00DCH address Bit [4:0] 00DCH address Bit [4:0] Gain set address address (00DDH address is set to...
Page 695 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 110 Relationship between Transmission Output Power and Gain Set Output power characteristic 0 10 20 30 40 50 60 70 80 90 100 110 Gain Set R01UH0575EJ0120 Rev. 1.20 Page 677 of 920...
Page 696 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 26 Gain Set (Frequency band identifier = 8) (1/3) 0090H 0092H 00DCH address Bit [7:4] 00DCH address Bit [4:0] 00DCH address Bit [4:0] Gain set address address (00DDH address is set to...
Page 697 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 27 Gain Set (Frequency band identifier = 8) (2/3) 0090H 0092H 00DCH address Bit [7:4] 00DCH address Bit [4:0] 00DCH address Bit [4:0] Gain set address address (00DDH address is set to...
Page 698 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 28 Gain Set (Frequency band identifier = 8) (3/3) 0090H 0092H 00DCH address Bit [7:4] 00DCH address Bit [4:0] 00DCH address Bit [4:0] Gain set address address (00DDH address is set to...
Page 699 RL78/G1H CHAPTER 18 RF TRANSCEIVER Figure 18 - 111 Relationship between Transmission Output Power and Gain Set (Frequency band identifier = 8) Output power characteristic 0 10 20 30 40 50 60 70 80 90 100 110 Gain Set (2) RF frequency setting for transmission Following descriptions are detail of <2>...
Page 700 RL78/G1H CHAPTER 18 RF TRANSCEIVER (3) RF frequency setting for reception Following descriptions are detail of <2> frequency setting in 18.7.1 (2) Example of procedure for RF reception. <1> Set 18.4.3 (53) BBFREQ register according to the RF frequency of reception.
Page 701 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 29 RF Frequency Set (Frequency band identifier = 4, Mode = 001) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 863.0000 863.5875 863.6000 864.4000...
Page 702 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 32 RF Frequency Set (Frequency band identifier = 5, Mode = 004) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 896.0000 896.0125 896.0250 896.1750...
Page 703 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 34 RF Frequency Set (Frequency band identifier = 5, Mode = 006) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 896.0000 896.0625 896.0750 896.7250...
Page 704 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 38 RF Frequency Set (Frequency band identifier = 7, Mode = 010) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 902.0000 902.1375 902.1500 903.8500...
Page 705 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 39 RF Frequency Set (Frequency band identifier = 7, Mode = 011) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 902.0000 902.2625 902.2750 903.7250...
Page 706 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 40 RF Frequency Set (Frequency band identifier = 7, Mode = 012) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 902.0000 902.3500 902.3625 903.6375...
Page 707 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 41 RF Frequency Set (Frequency band identifier = 8, Mode = 013) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 917.0000 917.8500 917.8625 918.1375...
Page 708 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 45 RF Frequency Set (Frequency band identifier = 9, Mode = 000) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 920.0000 920.2750 920.2875 921.7125...
Page 709 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 47 RF Frequency Set (Frequency band identifier = 9, Mode = 018) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 920.0000 920.4750 920.4875 921.5125...
Page 710 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 49 RF Frequency Set (Frequency band identifier = Other, Mode = 020) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 902.0000 902.1750 902.1875 903.8125...
Page 711 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 50 RF Frequency Set (Frequency band identifier = Other, Mode = 021) RF frequency set Lower limit RF frequency [MHz] Upper limit RF frequency [MHz] 0095H address Bit [7:0] 902.0000 902.3875 902.4000 902.5250...
Page 712: Setting For Each Data Rate
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.7.3 Setting for each data rate The list of each data rate is shown in Table 18 - 51 and the settings required for each data rate is listed in Table 18 - 52 to Table 18 - 59. Set values to addresses listed in Table 18 - 52 to Table 18 - 59 from the left in order according to the desired data rate in IDLE mode.
Page 713 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 52 Settings Required for Each Data Rate (1/9) Address (H) Frequency Data 00B2 00CE band Mode rate 000E 00B1 00AC 00AD 00CC identifier (kbps) Diversity: Diversity: Diversity: Diversity: 863 MHz (Europe) 896 MHz...
Page 714 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 53 Settings Required for Each Data Rate (2/9) Address (H) Frequency Data 0044 0110 band Mode rate 00C0 00C6 00C2 00C3 00C4 00C5 identifier (kbps) FEC: FEC: FEC: FEC: Enable Disable Enable...
Page 715 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 54 Settings Required for Each Data Rate (3/9) Address (H) Frequency Data 042D 0457 0458 band Mode rate 0430 0432 0422 043A identifier (kbps) Diversity: FEC: FEC: FEC: FEC: Diversity: Enable Disable...
Page 716 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 55 Settings Required for Each Data Rate (4/9) Address (H) Frequency Data band Mode rate 0423 0454 0456 0474 047C 047D 047F 0480 0483 0486 0487 identifier (kbps) 863 MHz (Europe) 896 MHz...
Page 717 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 56 Settings Required for Each Data Rate (5/9) Address (H) Frequency Data band Mode rate 048D 048F 0491 0492 0493 0494 0581 0582 058F 059F 05A0 identifier (kbps) 863 MHz (Europe) 896 MHz...
Page 718 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 57 Settings Required for Each Data Rate (6/9) Address (H) Frequency Data band Mode rate 05A1 05A2 0405 04F6 04F8 0505 0403 0415 04D9 0100 0101 identifier (kbps) 863 MHz (Europe) 896 MHz...
Page 719 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 58 Settings Required for Each Data Rate (7/9) Address (H) Frequency Data band Mode rate 0102 0103 0104 0105 0106 0107 0108 0109 010A 010B 00DC identifier (kbps) 863 MHz (Europe) 896 MHz...
Page 720 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 59 Settings Required for Each Data Rate (8/9) Address (H) Frequency Data band Mode rate 00DD 00DC 00DD 00F1 00F2 00F3 00F4 00F5 00FB 00DC 00DD identifier (kbps) 863 MHz (Europe) 896 MHz...
Page 721 RL78/G1H CHAPTER 18 RF TRANSCEIVER Table 18 - 60 Settings Required for Each Data Rate (9/9) Address (H) Frequency Data band Mode rate 00DC 00DD 00DC 00DD 00DC 00DD identifier (kbps) 863 MHz Note 1 Note 2 Note 3 (Europe)
Page 722: Notice For Using Baseband Function
RL78/G1H CHAPTER 18 RF TRANSCEIVER 18.8 Notice For Using Baseband Function 18.8.1 Notice About Transmission Do not stop transmit operation. Reset (initialize) by RFRESETB pin after setting RFSTOP bit to 1 for stopping transmission. Initialize in same way for stopping in continuous transmission mode and special transmission mode.
Page 723: Interrupt Functions
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS CHAPTER 19 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product.
Page 724 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Table 19 - 1 Interrupt Source List (1/2) Interrupt Source Name Trigger INTWDTI Note 3 Watchdog timer interval 0004H (75% of overflow time + 1/2 f INTLVI Note 4 0006H Voltage detection INTP0 Pin input edge detection...
Page 725 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Table 19 - 2 Interrupt Source List (2/2) Interrupt Source Name Trigger INTTM10 End of timer channel 10 count or capture 0042H INTTM11 End of timer channel 11 count or capture 0044H INTTM12 End of timer channel 12 count or capture...
Page 726 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 1 Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Priority controller Interrupt request address generator Standby release signal (B) External maskable interrupt (INTPn) Internal bus...
Page 727: Registers Controlling Interrupt Functions
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) • IInterrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) •...
Page 728 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Table 19 - 4 Flags Corresponding to Interrupt Request Sources (2/3) Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Interrupt Source Register Register Register Note 1 Note 1 IF1L Note 1 MK1L Note 1...
Page 729 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Table 19 - 5 Flags Corresponding to Interrupt Request Sources (3/3) Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Interrupt Source Register Register Register INTTM11 TMIF11 IF2L TMMK11 MK2L TMPR011, TMPR111 PR02L, PR12L INTTM12...
Page 730: Interrupt Request Flag Registers (If0L, If0H, If1L, If1H, If2L, If2H)
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 731 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 3 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2) Address: FFFD1H After reset: 00H Symbol <7> <6> <4> <0> SREIF3 IF2H FLIF IICAIF1 PIF11 TMIF13H XXIFX Interrupt request flag...
Page 732: Interrupt Mask Flag Registers (Mk0L, Mk0H, Mk1L, Mk1H, Mk2L, Mk2H)
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt. The MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 733 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 5 Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) (2/2) Address: FFFD5H After reset: FFH Symbol <7> <6> <4> <0> SREMK3 MK2H FLMK IICAMK1 PMK11 TMMK13H XXMKX Interrupt servicing control...
Page 734: Priority Specification Flag Registers (Pr00L, Pr00H, Pr01L, Pr01H, Pr02L, Pr02H, Pr10L, Pr10H, Pr11L, Pr11H, Pr12L, Pr12H)
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
Page 735 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 7 Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (2/2) Address: FFFEEH After reset: FFH Symbol <7> <6> <5> <4> <3> <2>...
Page 736: External Interrupt Rising Edge Enable Registers (Egp0, Egp1), External Interrupt Falling Edge Enable Registers (Egn0, Egn1)
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.3.4 External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers (EGN0, EGN1) These registers specify the valid edge for INTPn pin. The EGP0, EGP1, EGN0, and EGN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 737 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Table 19 - 6 shows the Ports Corresponding to EGPn and EGNn bits. Table 19 - 6 Ports Corresponding to EGPn and EGNn bits Detection Enable Bit Interrupt Request Signal EGP0 EGN0 INTP0 EGP3 EGN3...
Page 738: Program Status Word (Psw)
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.
Page 739: Interrupt Servicing Operations
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 740 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 10 Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending (xxPR1, xxPR0) No (Low priority) ≤ (ISP1, ISP0) Interrupt request held pending...
Page 741 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 11 Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction Instruction jump to interrupt servicing program xxIF 9 clocks Remark 1 clock: 1/f...
Page 742: Software Interrupt Request Acknowledgment
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
Page 743 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Table 19 - 8 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Software...
Page 744 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 13 Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice INTxx servicing INTyy servicing INTzz servicing Main processing IE = 0 IE = 0 IE = 0 INTxx...
Page 745 RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 - 14 Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00)
Page 746: Interrupt Servicing During Division Instruction
19.4.4 Interrupt servicing during division instruction The RL78/G1H handles interrupts during the DIVHU/DIVWU instruction in order to enhance the interrupt response when a division instruction is executed. • When an interrupt is generated while the DIVHU/DIVWU instruction is executed, the instruction is suspended •...
Page 747 For the following compilers, when DIVHU and DIVWU instructions are output at building, NOP instruction is automatically inserted right after the output. • CA78K0R (compiler product manufactured by Renesas Electronics Corporation) V1.71 or later: C language source and assembly language source •...
Page 748: Interrupt Request Hold
RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS 19.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 749: Standby Function
RL78/G1H CHAPTER 20 STANDBY FUNCTION CHAPTER 20 STANDBY FUNCTION 20.1 Standby Function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, high-speed on-chip oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 750: Registers Controlling Standby Function
RL78/G1H CHAPTER 20 STANDBY FUNCTION Caution 1. The STOP mode can be used only when the CPU is operating on the main system clock. Do not set to the STOP mode while the CPU operates with the subsystem clock. The HALT mode can be used when the CPU is operating on either the main system clock or the subsystem clock.
Page 751: Standby Function Operation
RL78/G1H CHAPTER 20 STANDBY FUNCTION 20.3 Standby Function Operation 20.3.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, or subsystem clock.
Page 752 RL78/G1H CHAPTER 20 STANDBY FUNCTION Table 20 - 1 Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction is Executed While CPU is Operating on Main System Clock When CPU is Operating on High- When CPU is Operating...
Page 753 RL78/G1H CHAPTER 20 STANDBY FUNCTION Table 20 - 2 Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction is Executed While CPU is Operating on Subsystem Clock When CPU is Operating on XT1 Clock When CPU is Operating on External...
Page 754 RL78/G1H CHAPTER 20 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Page 755 RL78/G1H CHAPTER 20 STANDBY FUNCTION Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Page 756: Stop Mode
RL78/G1H CHAPTER 20 STANDBY FUNCTION Figure 20 - 3 HALT Mode Release by Reset (2/2) (3) When subsystem clock is used as CPU clock HALT instruction Reset signal Normal operation mode Normal operation Reset (high-speed on-chip (subsystem clock) HALT mode...
Page 757 RL78/G1H CHAPTER 20 STANDBY FUNCTION Table 20 - 3 Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction is Executed While CPU is Operating on Main System Clock When CPU is Operating on When CPU is Operating on...
Page 758 RL78/G1H CHAPTER 20 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two sources. Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 759 RL78/G1H CHAPTER 20 STANDBY FUNCTION Figure 20 - 5 STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (X1 oscillation) is used as CPU clock Interrupt STOP request instruction Note 1 Standby release signal Note 2...
Page 760 RL78/G1H CHAPTER 20 STANDBY FUNCTION Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Page 761: Snooze Mode
RL78/G1H CHAPTER 20 STANDBY FUNCTION 20.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for the A/D converter, or DTC. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock.
Page 762 RL78/G1H CHAPTER 20 STANDBY FUNCTION Table 20 - 4 Operating Statuses in SNOOZE Mode STOP Mode Setting During STOP mode, receiving data signal from CSIp and UARTq, inputting timer trigger signal to A/D converter, and generating DTC activation by interrupt...
Page 763 RL78/G1H CHAPTER 20 STANDBY FUNCTION (2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode Figure 20 - 7 When the Interrupt Request Signal is Generated in the SNOOZE Mode STOP Trigger instruction detection Interrupt request...
Page 764: Reset Function
RL78/G1H CHAPTER 21 RESET FUNCTION CHAPTER 21 RESET FUNCTION The following seven operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit...
Page 765 RL78/G1H CHAPTER 21 RESET FUNCTION Figure 21 - 1 Block Diagram of Reset Function Internal bus Reset control flag register (RESF) TRAP WDTRF RPERF IAWRF LVIRF Watchdog timer reset signal Clear Clear Clear Clear Clear Reset signal by execution of illegal instruction...
Page 766: Timing Of Reset Operation
RL78/G1H CHAPTER 21 RESET FUNCTION 21.1 Timing of Reset Operation This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
Page 767 RL78/G1H CHAPTER 21 RESET FUNCTION Note 1. When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummy-output as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a reset signal to an external device, set P130 to high-level output by software.
Page 768 RL78/G1H CHAPTER 21 RESET FUNCTION Table 21 - 1 Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (the X1 and X2 pins are input port mode)
Page 769 RL78/G1H CHAPTER 21 RESET FUNCTION Table 21 - 2 Hardware Statuses After Reset Acknowledgment Hardware Note After Reset Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW)
Page 770: Register For Confirming Reset Source
RL78/G1H CHAPTER 21 RESET FUNCTION 21.2 Register for Confirming Reset Source 21.2.1 Reset control flag register (RESF) Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request.
Page 771 RL78/G1H CHAPTER 21 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 21 - 3. Table 21 - 3 RESF Register Status When Reset Request Is Generated Reset Source Reset by...
Page 772 RL78/G1H CHAPTER 21 RESET FUNCTION Figure 21 - 5 Procedure for Checking Reset Source After reset acceptance Read the RESF register (clear the RESF register) and Read RESF register store the value of the RESF register in any RAM. TRAP of RESF...
Page 773: Power-On-Reset Circuit
RL78/G1H CHAPTER 22 POWER-ON-RESET CIRCUIT CHAPTER 22 POWER-ON-RESET CIRCUIT 22.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions. • Generates internal reset signal at power on. The reset signal is released when the supply voltage (V ) exceeds the detection voltage (V ).
Page 774: Configuration Of Power-On-Reset Circuit
RL78/G1H CHAPTER 22 POWER-ON-RESET CIRCUIT 22.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 22 - 1. Figure 22 - 1 Block Diagram of Power-on-reset Circuit Internal reset signal Reference voltage source 22.3 Operation of Power-on-reset Circuit The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown next.
Page 775 RL78/G1H CHAPTER 22 POWER-ON-RESET CIRCUIT Figure 22 - 2 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/3) (1) When using an external reset by the RESET pin Supply voltage Note 5 Note 5 Operating voltage range lower limit = 1.51 V (TYP.)
Page 776 RL78/G1H CHAPTER 22 POWER-ON-RESET CIRCUIT Figure 22 - 3 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (2) LVD is interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (V...
Page 777 RL78/G1H CHAPTER 22 POWER-ON-RESET CIRCUIT Figure 22 - 4 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3) (3) LVD reset mode (option byte 000C1H: LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Operating voltage range lower limit = 1.51 V (TYP.)
Page 778: Voltage Detector
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR CHAPTER 23 VOLTAGE DETECTOR 23.1 Functions of Voltage Detector The operation mode and detection voltages (V ) for the voltage detector is set by using the option LVDH LVDL byte (000C1H). The voltage detector (LVD) has the following functions.
Page 779: Configuration Of Voltage Detector
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR 23.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 23 - 1. Figure 23 - 1 Block Diagram of Voltage Detector N-ch Internal reset signal LVDH LVDL INTLVI...
Page 780: Voltage Detection Register (Lvim)
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR 23.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 781: Voltage Detection Level Register (Lvis)
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR 23.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation input sets this register to 00H/01H/81H...
Page 782: Operation Of Voltage Detector
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR 23.4 Operation of Voltage Detector 23.4.1 When used as reset mode Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V ) by using the option byte 000C1H.
Page 783 RL78/G1H CHAPTER 23 VOLTAGE DETECTOR Figure 23 - 4 Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.)
Page 784: When Used As Interrupt Mode
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR 23.4.2 When used as interrupt mode Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (V ) by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt mode is set.
Page 785 RL78/G1H CHAPTER 23 VOLTAGE DETECTOR Figure 23 - 5 Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Note 2 Note 2 Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.)
Page 786: When Used As Interrupt And Reset Mode
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR 23.4.3 When used as interrupt and reset mode Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (V LVDH ) by using the option byte 000C1H. LVDL The operation is started in the following initial setting state when the interrupt &...
Page 787 RL78/G1H CHAPTER 23 VOLTAGE DETECTOR Figure 23 - 6 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask , determine that a condition of V...
Page 788 RL78/G1H CHAPTER 23 VOLTAGE DETECTOR Note 1. The LVIMK flag is set to “1” by reset signal generation. Note 2. After an interrupt is generated, perform the processing according to Figure 23 - 8 Setting Procedure for Operating Voltage Check and Reset in interrupt and reset mode.
Page 789 RL78/G1H CHAPTER 23 VOLTAGE DETECTOR Figure 23 - 7 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of V is V < V after releasing the mask, LVDH a reset is generated because of LVIMD = 1 (reset mode).
Page 790 RL78/G1H CHAPTER 23 VOLTAGE DETECTOR Note 1. The LVIMK flag is set to “1” by reset signal generation. Note 2. After an interrupt is generated, perform the processing according to Figure 23 - 8 Setting Procedure for Operating Voltage Check and Reset in interrupt and reset mode.
Page 791: Cautions For Voltage Detector
RL78/G1H CHAPTER 23 VOLTAGE DETECTOR 23.5 Cautions for Voltage Detector (1) Voltage fluctuation when power is supplied In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVD detection voltage, the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 792 RL78/G1H CHAPTER 23 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (V ) < LVD detection voltage (V ) until the time LVD reset has been generated.
Page 793: Safety Functions
(1) Flash memory CRC operation function (high-speed CRC, general-purpose CRC) This detects data errors in the flash memory by performing CRC operations. Two CRC functions are provided in the RL78/G1H that can be used according to the application or purpose of use.
Page 794: Registers Used By Safety Functions
The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The high-speed CRC provided in the RL78/G1H can be used to check the entire code flash memory area during the initialization routine. The high-speed CRC can be executed only when the program is allocated on the RAM and in the HALT mode of the main system clock.
Page 795 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.1.1 Flash memory CRC control register (CRC0CTL) This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range. The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 796 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.1.2 Flash memory CRC operation result register (PGCRCL) This register is used to store the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H.
Page 797 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS <Operation flow> Figure 24 - 3 Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits ;...
Page 798: Crc Operation Function (General-Purpose Crc)
CPU is operating. In the RL78/G1H, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked can be specified by using software (a user-created program).
Page 799 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.2.1 CRC input register (CRCIN) CRCIN register is an 8-bit register that is used to set the CRC operation data of general-purpose CRC. The possible setting range is 00H to FFH. The CRCIN register can be set by an 8-bit memory manipulation instruction.
Page 800 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.2.2 CRC data register (CRCD) This register is used to store the general-purpose CRC operation result. The possible setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (f ) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register.
Page 801: Ram Parity Error Detection Function
The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/G1H’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error occurs.
Page 802 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS Figure 24 - 8 RAM Parity Error Check Flow Check start Note RPERF = 1 Disable parity error resets RPERDIS = 1 RAM check Read RAM RAM check Parity error has RPEF = 1 Confirm that a parity occurred error has occurred.
Page 803: Ram Guard Function
RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space.
Page 804: Sfr Guard Function
RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function.
Page 805: Invalid Memory Access Detection Function
RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed.
Page 806 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.6.1 Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function. The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Page 807: Frequency Detection Function
RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (f and measuring the pulse width of the input signal CLK) to channel 1 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined.
Page 808 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.7.1 Timer input select register 0 (TIS0) The TIS0 register is used to select the timer input of channels 0 and 1 of the timer array unit 0 (TAU0). The TIS0 register can be set by an 8-bit memory manipulation instruction.
Page 809: A/D Test Function
RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function is used to check whether the A/D converter is operating normally by executing A/D conversions of the positive reference voltage and negative reference voltage of the A/D converter, analog input channel (ANI).
Page 810 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS Figure 24 - 15 Configuration of A/D Test Function •ADS4 to 0 ANI0/AV REFP ANI1/AV REFM ANIxx • ADTES1 to 0 ANIxx A/D convertor + side reference voltage • ADREFP0 A/D convertor A/D convertor - side reference voltage •...
Page 811 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.8.1 A/D test register (ADTES) This register is used to select the A/D converter positive reference voltage, negative reference voltage, analog input channel (ANIxx) as the target of A/D conversion. When using the A/D test function, specify the following settings: •...
Page 812 RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.8.2 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. Set A/D test register (ADTES) to 00H when measuring the ANIxx. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 813: Digital Output Signal Level Detection Function For I/O Pins
RL78/G1H CHAPTER 24 SAFETY FUNCTIONS 24.3.9 Digital output signal level detection function for I/O pins In the IEC60730, it is required to check that the I/O function correctly operates. By using the digital output signal level detection function for I/O pins, the digital output level of the pin can be read when the port is set to output mode.
Page 814: Regulator
25.1 Regulator Overview The RL78/G1H contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1 μF). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
Page 815: Option Byte
RL78/G1H CHAPTER 26 OPTION BYTE CHAPTER 26 OPTION BYTE 26.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Page 816: On-Chip Debug Option Byte (000C3H/ 010C3H)
RL78/G1H CHAPTER 26 OPTION BYTE (3) 000C2H/010C2H Setting of flash operation mode • LS (low-speed main) mode • HS (high-speed main) mode Setting of the frequency of the high-speed on-chip oscillator • Select from 1 MHz to 32 MHz. Caution Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H.
Page 817: Format Of User Option Byte
RL78/G1H CHAPTER 26 OPTION BYTE 26.2 Format of User Option Byte The format of user option byte is shown below. Figure 26 - 1 Format of User Option Byte (000C0H/010C0H) Note 1 Address: 000C0H/010C0H WDTINT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1...
Page 818 RL78/G1H CHAPTER 26 OPTION BYTE Note 3. When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to <R> WDTE) must proceed outside the corresponding period from among those listed below, over which clearing of the counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of the watchdog timer is set).
Page 819 RL78/G1H CHAPTER 26 OPTION BYTE Figure 26 - 3 Format of User Option Byte (000C1H/010C1H) (2/4) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (reset mode) Detection voltage Option byte Setting Value Mode setting VPOC2...
Page 820 RL78/G1H CHAPTER 26 OPTION BYTE Figure 26 - 4 Format of User Option Byte (000C1H/010C1H) (3/4) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode) Detection voltage Option byte Setting Value Mode setting VPOC2...
Page 821 RL78/G1H CHAPTER 26 OPTION BYTE Figure 26 - 5 Format of User Option Byte (000C1H/010C1H) (4/4) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD off setting (external reset input from the RESET pin is used) Detection voltage...
Page 822 RL78/G1H CHAPTER 26 OPTION BYTE Figure 26 - 6 Format of Option Byte (000C2H/010C2H) Note Address: 000C2H/010C2H CMODE1 CMODE0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Setting of flash operation mode CMODE1 CMODE0 Operating Operating Voltage Range Frequency Range LS (low-speed main) mode 1 to 8 MHz 1.8 to 3.6 V...
Page 823: Format Of On-Chip Debug Option Byte
RL78/G1H CHAPTER 26 OPTION BYTE 26.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 26 - 7 Format of On-chip Debug Option Byte (000C3H/010C3H) Note Address: 000C3H/010C3H OCDENSET OCDERSD OCDENSET OCDERSD Control of on-chip debug operation Disables on-chip debug operation.
Page 824: Flash Memory
RL78/G1H CHAPTER 27 FLASH MEMORY CHAPTER 27 FLASH MEMORY The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data.
Page 825: Serial Programming Using Flash Memory Programmer
Remark FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd. Table 27 - 1 Wiring Between RL78/G1H and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Signal Name Pin Name Pin No.
Page 826: Programming Environment
RL78/G1H CHAPTER 27 FLASH MEMORY 27.1.1 Programming Environment The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below. Figure 27 - 1 Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 RS-232C...
Page 827 RL78/G1H CHAPTER 27 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See the manual of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details. Table 27 - 2 Pin Connection Dedicated Flash Memory Programmer...
Page 828: Connection Of Pins On Board
RL78/G1H CHAPTER 27 FLASH MEMORY 27.2 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 829: Port Pins
RL78/G1H CHAPTER 27 FLASH MEMORY 27.2.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port...
Page 830: Programming Method
RL78/G1H CHAPTER 27 FLASH MEMORY 27.3 Programming Method 27.3.1 Serial programming procedure The following figure illustrates a flow for rewriting the code flash memory through serial programming. Figure 27 - 4 Code Flash Memory Manipulation Procedure Start Flash memory programming...
Page 831: Flash Memory Programming Mode
RL78/G1H CHAPTER 27 FLASH MEMORY 27.3.2 Flash memory programming mode To rewrite the contents of the code flash memory through serial programming, specify the flash memory programming mode. To enter the mode, set as follows. <When serial programming by using the dedicated flash memory programmer>...
Page 832 RL78/G1H CHAPTER 27 FLASH MEMORY There are two flash memory programming modes: wide voltage mode and full speed mode. The supply voltage value applied to the microcontroller during write operations and the setting information of the user option byte for setting of the flash memory programming mode determine which mode is selected.
Page 833: Selecting Communication Mode
RL78/G1H CHAPTER 27 FLASH MEMORY 27.3.3 Selecting communication mode Communication mode of the RL78 microcontroller as follows. Table 27 - 5 Communication Modes Note 1 Standard Setting Communication Mode Pins Used Port Note 2 Frequency Multiply Rate Speed 1-line mode...
Page 834: Communication Commands
RL78/G1H CHAPTER 27 FLASH MEMORY 27.3.4 Communication commands The RL78 microcontroller executes serial programming through the commands listed in Table 27 - 6. The signals sent from the dedicated flash memory programmer or external device to the RL78 microcontroller are called commands, and programming functions corresponding to the commands are executed. For details, refer to the RL78 microcontroller (RL78 Protocol A) Programmer Edition Application Note (R01AN0815).
Page 835: Processing Time For Each Command When Pg-Fp5 Is In Use (Reference Value)
RL78/G1H CHAPTER 27 FLASH MEMORY 27.4 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) The following shows the processing time for each command (reference value) when PG-FP5 is used as a dedicated flash memory programmer. Table 27 - 8 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value)
Page 836: Self-Programming
LS (low-speed main) mode is specified. If the argument fsl_flash_voltage_u08 is 00H when the FSL_Init function of the flash self-programming library provided by Renesas Electronics is executed, full speed mode is specified. If the argument is other than 00H, the wide voltage mode is specified.
Page 837: Self-Programming Procedure
RL78/G1H CHAPTER 27 FLASH MEMORY 27.5.1 Self-programming procedure The following figure illustrates a flow for rewriting the code flash memory by using a flash self-programming library. Figure 27 - 6 Flow of Self-Programming (Rewriting Flash Memory) Code flash memory control start...
Page 838: Boot Swap Function
RL78/G1H CHAPTER 27 FLASH MEMORY 27.5.2 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem.
Page 839 RL78/G1H CHAPTER 27 FLASH MEMORY Figure 27 - 8 Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 User program User program User program User program User program User program...
Page 840: Flash Shield Window Function
RL78/G1H CHAPTER 27 FLASH MEMORY 27.5.3 Flash shield window function The flash shield window function is provided as one of the security functions for self-programming. It disables writing to and erasing areas outside the range specified as a window only during self-programming.
Page 841: Security Settings
RL78/G1H CHAPTER 27 FLASH MEMORY 27.6 Security Settings The RL78 microcontroller supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command.
Page 842 RL78/G1H CHAPTER 27 FLASH MEMORY Table 27 - 10 Relationship Between Enabling Security Function and Command (1) During serial programming Executed Command Valid Security Block Erase Write Prohibition of block erase Blocks cannot be erased. Note Can be performed. Prohibition of writing Blocks can be erased.
Page 843: Data Flash
RL78/G1H CHAPTER 27 FLASH MEMORY 27.7 Data Flash 27.7.1 Data flash overview An overview of the data flash memory is provided below. • The user program can rewrite the data flash memory by using the flash data library. For details, refer to RL78 Family Data Flash Library User’s Manual.
Page 844: Register Controlling Data Flash Memory
RL78/G1H CHAPTER 27 FLASH MEMORY 27.7.2 Register controlling data flash memory 27.7.2.1 Data flash control register (DFLCTL) This register is used to enable or disable accessing to the data flash. The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Page 845: Procedure For Accessing Data Flash Memory
RL78/G1H CHAPTER 27 FLASH MEMORY 27.7.3 Procedure for accessing data flash memory The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To access the memory, perform the following procedure: <1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).
Page 846: On-Chip Debug Function
Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 847: On-Chip Debug Security Id
To perform communication between the RL78 microcontroller and E1 on-chip debugging emulator, as well as each debug function, the securing of memory space must be done beforehand. If Renesas Electronics assembler or compiler is used, the items can be set by using link options. (1) Securement of memory space The shaded portions in Figure 28 - 2 are the areas reserved for placing the debug monitor program, so user programs or data cannot be allocated in these spaces.
Page 848 RL78/G1H CHAPTER 28 ON-CHIP DEBUG FUNCTION Figure 28 - 2 Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area Note 1 (512 bytes or Note 2 256 bytes Internal RAM Stack area for debugging...
Page 849: Bcd Correction Circuit
RL78/G1H CHAPTER 29 BCD CORRECTION CIRCUIT CHAPTER 29 BCD CORRECTION CIRCUIT 29.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ).
Page 850: Bcd Correction Circuit Operation
RL78/G1H CHAPTER 29 BCD CORRECTION CIRCUIT 29.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
Page 851 RL78/G1H CHAPTER 29 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.
Page 852: Instruction Set
RL78/G1H CHAPTER 30 INSTRUCTION SET CHAPTER 30 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Family User’s Manual Software (R01US0015). R01UH0575EJ0120 Rev. 1.20...
Page 853: Conventions Used In Operation List
RL78/G1H CHAPTER 30 INSTRUCTION SET 30.1 Conventions Used in Operation List 30.1.1 Operand identifiers and specification methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them.
Page 854: Description Of Operation Column
RL78/G1H CHAPTER 30 INSTRUCTION SET 30.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 30 - 2 Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator...
Page 855: Description Of Flag Operation Column
RL78/G1H CHAPTER 30 INSTRUCTION SET 30.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 30 - 3 Symbols in “Flag” Column...
Page 856: Operation List
RL78/G1H CHAPTER 30 INSTRUCTION SET 30.2 Operation List Table 30 - 5 Operation List (1/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit data r, #byte — r ← byte transfer × × × PSW, #byte —...
Page 857 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 6 Operation List (2/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit data A, sfr — A ← sfr transfer sfr, A — sfr ← A A, [DE] A ←...
Page 858 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 7 Operation List (3/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit data A, [HL+B] A ← (HL + B) transfer [HL+B], A — (HL + B) ← A A, ES:[HL+B] A ←...
Page 859 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 8 Operation List (4/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit data A, [HL+B] — A ←→ (HL + B) transfer A, ES:[HL+B] — A ←→ ((ES, HL) + B) A, [HL+C] —...
Page 860 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 9 Operation List (5/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 16-bit data MOVW AX, [DE] AX ← (DE) transfer [DE], AX — (DE) ← AX AX, ES:[DE] AX ←...
Page 861 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 10 Operation List (6/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 16-bit data MOVW BC, !addr16 BC ← (addr16) transfer BC, ES:!addr16 BC ← (ES, addr16) DE, !addr16 DE ←...
Page 862 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 11 Operation List (7/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit ADDC A, #byte — A, CY ← A + byte + CY × × ×...
Page 863 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 12 Operation List (8/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit SUBC A, #byte — A, CY ← A - byte - CY × × ×...
Page 864 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 13 Operation List (9/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit A, #byte — A ← A ∨ byte × operation saddr, #byte — (saddr) ← (saddr) ∨ byte ×...
Page 865 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 14 Operation List (10/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 8-bit A, #byte — A - byte × × × operation !addr16, #byte (addr16) - byte ×...
Page 866 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 15 Operation List (11/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 16-bit ADDW AX, #word — AX, CY ← AX + word × × × operation AX, AX —...
Page 867 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 16 Operation List (12/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 Multiply, MULU — AX ← A × X Divide, MULHU — BCAX ← AX × BC (unsigned) Multiply &...
Page 868 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 17 Operation List (13/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 Increment/ — r ← r + 1 × × decrement !addr16 — (addr16) ← (addr16) + 1 ×...
Page 869 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 18 Operation List (14/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 Rotate A, 1 — (CY, A ← A ← A ) × 1 × m - 1 A, 1 —...
Page 870 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 19 Operation List (15/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 XOR1 CY, A.bit — CY ← CY ∨ A.bit × manipulate CY, PSW.bit — CY ← CY ∨ PSW.bit ×...
Page 871 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 20 Operation List (16/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 Call/return CALL — (SP - 2) ← (PC + 2) , (SP - 3) ← (PC + 2) (SP - 4) ←...
Page 872 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 21 Operation List (17/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 Stack PUSH (SP - 1) ← PSW, (SP - 2) ← 00H, — manipulate SP ← SP - 2 (SP - 1) ←...
Page 873 RL78/G1H CHAPTER 30 INSTRUCTION SET Table 30 - 22 Operation List (18/18) Clocks Flag Instruction Mnemonic Operands Bytes Clocks Group Note 1 Note 2 Conditional saddr.bit, $addr20 PC ← PC + 4 + jdisp8 if (saddr).bit = 0 Note 3 —...
Page 874: Electrical Specifications
Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 875: Absolute Maximum Ratings
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.1 Absolute Maximum Ratings Absolute Maximum Ratings (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage Note 1 ‒0.5 to +3.8 VCCRF, VCCDDC ‒0.3 to +3.8 Note 1 DDRF ‒0.3 to +0.3 VSSDDC, AGNDRF1, AGNDRF2, RFIN, ‒0.3 to +0.3...
Page 876 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (2/2) Parameter Symbols Conditions Ratings Unit REGC pin input voltage REGC ‒0.3 to +2.8 and IREGC Note ‒0.3 to V + 0.3 RF power supply input REGIN ‒0.3 to +3.8 REGIN RF power supply output DDCOUT ‒0.3 to +3.8...
Page 877: Oscillator Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.2 Oscillator Characteristics 31.2.1 X1, XT1 characteristics 40 to +85 °C, 1.8 V ≤ V ≤ 3.6 V, V = 0 V) ‒ Resonator Resonator Conditions MIN. TYP. MAX. Unit Ceramic resonator/ 20.0 Note 2.7 V ≤ V ≤...
Page 878: Dc Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.3 DC Characteristics 31.3.1 Pin characteristics 40 to +85 °C, 1.8 V 3.6 V, V = 0 V) (1/5) ≤ ≤ ‒ Items Symbol Conditions MIN. TYP. MAX. Unit Per pin for P02 to P04, P31, ‒10.0...
Page 879 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS = ‒40 to +85 °C, 1.8 V ≤ V ≤ 3.6 V, V = 0 V) (2/5) Items Symbol Conditions MIN. TYP. MAX. Unit Per pin for P02 to P04, P31, P40, 20.0 Note 1...
Page 880 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS = ‒40 to +85 °C, 1.8 V ≤ V ≤ 3.6 V, V = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high P02 to P04, P31, P40, Normal input buffer 0.8 V...
Page 881 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS = ‒40 to +85 °C, 1.8 V ≤ V ≤ 3.6 V, V = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high P02 to P04, P31, P40, 2.7 V ≤ V ≤...
Page 882 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS = ‒40 to +85 °C, 1.8 V ≤ V ≤ 3.6 V, V = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage P02 to P04, P31, P40, μA LIH1 current, high...
Page 883: Supply Current Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.3.2 Supply current characteristics 40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ‒ ≤ ≤ (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply Operating HS (high-speed Basic = 3.0 V...
Page 884 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Note 1. Total current flowing into V , including the input leakage current flowing when the level of the input pin is fixed to V . The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the RF transceiver, A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Page 885 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS = ‒40 to +85 °C, 1.8 V ≤ V ≤ 3.6 V, V = 0 V) (2/2) Parameter Symbo Conditions MIN. TYP. MAX. Unit Supply HALT mode HS (high-speed = 3.0 V 2.63 Note 4...
Page 886 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Note 1. Total current flowing into V , including the input leakage current flowing when the level of the input pin is fixed to V . The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the RF transceiver, A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Page 887 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Peripheral Functions (Common to all products) 40 to +85 °C, 1.8 V ≤ ≤ 3.6 V, V = 0 V) ‒ Parameter Symbol Conditions MIN. TYP. Unit Low-speed on-chip oscillator FIL Note 1 0.20 μA...
Page 888: Ac Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.4 AC Characteristics = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤ ≤ Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle Main system HS (high-speed main) 2.7 V ≤ V ≤...
Page 889 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Minimum Instruction Execution Time during Main System Clock Operation vs V (HS (high-speed main) mode) When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.0625 0.05 0.03125 0.01 Supply voltage V R01UH0575EJ0120 Rev.
Page 890 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS vs V (LS (low-speed main) mode) When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.125 0.01 Supply voltage V R01UH0575EJ0120 Rev. 1.20 Page 872 of 920 Dec 22, 2016...
Page 891 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS AC Timing Test Points Test points External System Clock Timing EXLS EXHS EXCLK/EXCLKS TI/TO Timing TI03 TO03 R01UH0575EJ0120 Rev. 1.20 Page 873 of 920 Dec 22, 2016...
Page 892 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Interrupt Request Input Timing INTL INTH INTP0, INTP4, INTP6, INTP7, INTP9 to INTP11 RESET Input Timing RESET R01UH0575EJ0120 Rev. 1.20 Page 874 of 920 Dec 22, 2016...
Page 893: Peripheral Functions Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.5 Peripheral Functions Characteristics AC Timing Test Points Test points 31.5.1 Serial array unit (1) During communication at same potential (UART mode) = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤...
Page 894 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remark 1. q: UART number (q = 1, 3), g: PIM and POM number (g = 0, 14) Remark 2.
Page 895 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) = ‒40 to +85 °C, 1.8 V ≤ ≤ 3.6 V, V = 0 V) Parameter Symbol Conditions HS (high-speed main)
Page 896 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) = ‒40 to +85 °C, 1.8 V ≤ ≤ 3.6 V, V = 0 V) Parameter Symbol Conditions HS (high-speed main)
Page 897 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY1, 2 KH1, 2 KL1, 2 SCKp KSI1, 2...
Page 898 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) = ‒40 to +85 °C, 1.8 V ≤ ≤ 3.6 V, V = 0 V) (1/2) Parameter Symbol Conditions HS (high-speed main)
Page 899 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) = ‒40 to +85 °C, 1.8 V ≤ V ≤ 3.6 V, V = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main)
Page 900 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V...
Page 901 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) (1/3) ≤ ≤...
Page 902 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) = -40 to +85 °C, 1.8 V 3.6 V, V = 0 V) (2/3) ≤ ≤...
Page 903 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) = -40 to +85 °C, 1.8 V 3.6 V, V = 0 V) (3/3) ≤ ≤...
Page 904 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) <Master> SCKp User’s device RL78 microcontroller Remark 1. R [Ω]: Communication line (SCKp, SOp) pull-up resistance, C [F]: Communication line (SCKp, SOp) load capacitance, V [V]: Communication line voltage Remark 2.
Page 905 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY1 SCKp SIK1 KSI1 Input data KSO1...
Page 906 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤ ≤ Parameter...
Page 907 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) <Slave> SCKp RL78 microcontroller User’s device Remark 1. R [Ω]: Communication line (SOp) pull-up resistance, C [F]: Communication line (SOp) load capacitance, [V]: Communication line voltage Remark 2.
Page 908 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY2 SCKp SIK2 KSI2 Input data KSO2...
Page 909: Serial Interface Iica
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.5.2 Serial interface IICA (1) I C standard mode = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤ ≤ Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) Unit mode mode MIN.
Page 910 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (2) I C fast mode = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤ ≤ Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) Unit mode mode MIN. MAX. MIN.
Page 911 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (3) I C fast mode plus = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤ ≤ Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) Unit mode mode MIN. MAX.
Page 912: Analog Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.6 Analog Characteristics 31.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AV Reference voltage (+) = V REFP Input channel Reference voltage (‒) = AV Reference voltage (‒) = V REFM ANI0 to ANI2, ANI13, ANI14, ANI19 Refer to 31.6.1 (1) .
Page 913: Por Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (2) When reference voltage (+) = V (ADREFP0 = 0), reference voltage (‒) = V (ADREFM = 0), target pin: ANI0 to ANI2, ANI13, ANI14, ANI19 = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V, Reference voltage (+) = V , Reference voltage (‒) = V...
Page 914: Lvd Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.6.3 LVD characteristics (1) Reset Mode and Interrupt Mode = ‒40 to +85 °C, V 3.6 V, V = 0 V) ≤ ≤ Parameter Symbol Conditions MIN. TYP. MAX. Unit Voltage Supply voltage level Rising edge 3.07...
Page 915: Power Supply Voltage Rising Slope Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS (2) Interrupt & Reset Mode = ‒40 to +85 °C, V ≤ ≤ 3.6 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Voltage detection = 0, 0, 1, falling reset voltage 1.80...
Page 916: Rf Transceiver Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.7 RF Transceiver Characteristics 31.7.1 Recommended operating conditions Parameter Conditions MIN. TYP. MAX. Unit Power supply voltage Operating ambient temperature ‒40 °C XIN frequency Operating frequency Channel interval 12.5/200/400/600 Data rate 2FSK/GFSK 10/20/40/50/100/150/200/300 kbps 4FSK/GFSK...
Page 917 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.7.2.2 Compatible with ARIB Standard XIN frequency accuracy is required according to the table below to satisfy the ARIB standard. Frequency Maximum Symbol rate Variable band frequency MIN. TYP. MAX. Unit [ksymbols/s] index [MHz] [MHz] ‒20...
Page 918: Dc Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.7.3 DC characteristics = 25 °C, V =3.0 V, V = 0 V) DDRF SSRF Parameter Symbol Conditions MIN. TYP. MAX. Unit High-level output GPIO0 to GPIO4 1.8V 3.6 V ‒2.0 ≤ ≤ OHRF DDRF...
Page 919: Transceiver Reception Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.7.5 Transceiver reception characteristics = 25 °C, V =3.0 V, V = 0 V) (1/2) DDRF SSRF Parameter Conditions MIN. TYP. MAX. Unit Reception sensitivity 2GFSK, BT = 0.5, BER < 0.1%, — ‒114 ‒109 10 kbps, m = 0.5...
Page 920: Transceiver Transmission Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS = 25 °C, V =3.0 V, V = 0 V) (2/2) DDRF SSRF Parameter Conditions MIN. TYP. MAX. Unit Suppression ±2 MHz Desired signal 3 dB above the input sensitivity — — ratio level, CW interferer, BER < 0.1% ±10 MHz...
Page 921: Ieee802.15.4G Frequency/Data Rate Table
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.7.7 IEEE802.15.4g frequency/data rate table Frequency Data Symbol Channel Total Channel 0 Frequency Operating Modulation band Modulation rate rate spacing number of frequency band (MHz) mode index identifier (kbps) (ksps) (kHz) channels (MHz) 863 MHz...
Page 922: Ac Characteristics
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.7.8 AC Characteristics = ‒40 °C, to +85 °C, 2.4 V 3.6 V, V = 0 V) ≤ ≤ DDRF SSRF Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKL cycle time tsccyc SEN setup time...
Page 923 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS = ‒40 °C, to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤ ≤ DDRF SSRF Parameter Symbol Conditions MIN. TYP. MAX. Unit STANDBYlow-level width tstbyl μs OSCDRVSEL setup time todssu Crystal resonator μs...
Page 924 RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS Figure 31 - 3 Timing input external clock tstbyl STANDBY OSCDRVSEL trfrstsu2 RFRESETB R01UH0575EJ0120 Rev. 1.20 Page 906 of 920 Dec 22, 2016...
Page 925: Ram Data Retention Characteristics
Note 2. When using flash memory programmer and Renesas Electronics self-programming library. Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 31.10 Dedicated Flash Memory Programmer Communication (UART) = -40 to +85 °C, 1.8 V...
Page 926: Timing For Switching Flash Memory Programming Modes
RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS 31.11 Timing for Switching Flash Memory Programming Modes = ‒40 to +85 °C, 1.8 V 3.6 V, V = 0 V) ≤ ≤ Parameter Symbol Conditions MIN. TYP. MAX. Unit How long from when an external reset ends until the...
Page 927: Package Drawing
9.10 8.90 9.00 9.10 1.00 0.00 0.20 0.25 0.30 0.50 0.30 0.40 0.50 0.05 0.05 S AB 0.75 0.75 0.20 6.90 6.90 © 2015 Renesas Electronics Corporation. All rights reserved. R01UH0575EJ0120 Rev. 1.20 Page 909 of 920 Dec 22, 2016...
Page 928: Appendix A Revision History
RL78/G1H APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY Major Revisions in This Edition (1/2) Page Description Classification CHAPTER 1 OUTLINE Change of Caution in 1.3 Pin Configuration (Top View) Change of 1.6 Outline of Functions CHAPTER 3 PIN FUNCTIONS p.23...
Page 929 RL78/G1H APPENDIX A REVISION HISTORY (2/2) Page Description Classification p.598 Addition of description to 18.4.4 (30) Baseband interrupt enable register 1 (BBINTEN1) and Figure 18 - 39 Baseband Interrupt Enable Register 1 (BBINTEN1) Format p.598 Change of Figure 18 - 39 Baseband Interrupt Enable Register 1 (BBINTEN1) Format p.599...
Page 930: A.2 Revision History Of Preceding Editions
Change of Figure 2 - 4 RL78/G1H (64-pin) Peripheral Circuits’Connection Diagram TRANSCEIVER (with ANTSW) Addition of Figure 2 - 5 RL78/G1H (64-pin) Peripheral Circuit Connection Diagram (Using TCXO) Change of Figure 4 - 1 Memory Map (R5F11FLJ) CHAPTER 4 CPU...
Page 931 RL78/G1H APPENDIX A REVISION HISTORY (2/9) Edition Description Chapter Rev1.00 Change of description in 18.4.4 (9) Transmit/receive mode register 3 CHAPTER 18 RF (BBTXRXMODE3) TRANSCEIVER Change of Figure 18 - 15 Transmit/Receive Mode Register 3 (BBTXRXMODE3) Format Change of description in 18.4.4 (10) Transmit/receive status register 1 (BBTXRXST1) Change of Figure 18 - 16 Transmit/Receive Status Register 1 (BBTXRXST1) Format Change of description in 18.4.4 (11) Transmit/receive control register (BBTXRXCON)
Page 932 RL78/G1H APPENDIX A REVISION HISTORY (3/9) Edition Description Chapter Rev1.00 Change of description in 18.4.4 (60) Mode switch frame receive register CHAPTER 18 RF (BBRXMODESW) TRANSCEIVER Change of description in 18.4.4 (61) Transmit data counter register (BBTXCOUNT) Change of description in 18.4.4 (62) PHY header receive register (BBPHRRX) Change of description in 18.4.4 (63) Preamble setting register (BBPABL)
Page 933 RL78/G1H APPENDIX A REVISION HISTORY (4/9) Edition Description Chapter Rev1.00 Addition of description to 18.6.1 (3) IDLE mode CHAPTER 18 RF Change of description in 18.6.3 State transition TRANSCEIVER Change of Figure 18 - 105 RF Unit State Transition Change of Figure 18 - 107 Wake Up Operation (for REFCLKIN_RF External Clock) Change of description in 18.6.4 Mode transition...
Page 934 RL78/G1H APPENDIX A REVISION HISTORY (5/9) Edition Description Chapter Rev.0.60 Deletion of note 1 in Table 4 - 7 Special Function Register (SFR) List (3/5) CHAPTER 4 CPU Change of Table 4 - 11 Extended Special Function Register (2nd SFR) List (2/7)
Page 935 RL78/G1H APPENDIX A REVISION HISTORY (6/9) Edition Description Chapter Rev.0.60 Addition of Figure 14 - 73 Initial Setting Procedure for UART Transmission CHAPTER 14 SERIAL Change of Figure 14 - 75 Procedure for Resuming UART Transmission ARRAY UNIT Change of remark in Figure 14 - 76 Timing Chart of UART Transmission (in Single-...
Page 936 RL78/G1H APPENDIX A REVISION HISTORY (7/9) Edition Description Chapter Rev.0.60 Change of description in 18.4.3 (2) Transmit/receive reset register (BBTXRXRST) CHAPTER 18 RF Change of description in 18.4.3 (9) Transmit/receive mode register 3 TRANSCEIVER (BBTXRXMODE3) Change of Figure 18 - 15 Transmit/Receive Mode Register 3 (BBTXRXMODE3) Format Deletion of description in 18.4.3(10) Transmit/receive status register 1 (BBTXRXST1)
Page 937 RL78/G1H APPENDIX A REVISION HISTORY (8/9) Edition Description Chapter Rev.0.60 Change of Figure 18 - 70 Antenna Diversity Mode Register (BBANTDIV) Format CHAPTER 18 RF Change of description in 18.4.3 (60) Transmit data counter register (BBTXCOUNT) TRANSCEIVER Change of description in 18.4.3 (63) SFD setting register (BBSFD) Change of description in 18.4.3 (68) Receive start timeout setting register...
Page 938 RL78/G1H APPENDIX A REVISION HISTORY (9/9) Edition Description Chapter Rev.0.60 Change of Figure 19 - 6, 19 - 7 Format of Priority Specification Flag Registers (PR00L, CHAPTER 19 PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, INTERRUPT PR12H)
Page 939 RL78/G1H User’s Manual: Hardware Publication Date: Rev. 0.50 Sep 18, 2015 Rev. 1.20 Dec 22, 2016 Published by: Renesas Electronics Corporation...
Page 940 Address List http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3...
Page 941 RL78/G1H R01UH0575EJ0120...