Renesas RL78/G1P Hardware User Manual page 558

RL78/G1P
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4)
(3) Data ~ data ~ Stop condition
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master
device.
2. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop
condition after a stop condition has been issued is at least 4.0
at least 0.6
3. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-32. Example of Master to Slave Communication
Note 1
<9>
H
H
L
L
<8>
D 0
ACK D 7
15
16
<7>
L
H
H
L
Note 3
<10>
L
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices

s when specifying fast mode.
CHAPTER 12 SERIAL INTERFACE IICA
Stop condition
D 6 D
D 5 D 4 D 3
16 16 16 16 16
<14>
<12>
2 D 1 D 0
ACK
16 16
Note 2
<11>
Note 3
<13>

s when specifying standard mode and
<15>
539