Renesas RL78/G1P Hardware User Manual page 504

RL78/G1P
12.4.2 Setting transfer clock by using IICWLn and IICWHn registers
(1) Setting transfer clock on master side
Transfer clock =
At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
(The fractional parts of all setting values are rounded up.)
 When the fast mode
Transfer clock  f
IICWLn =
Transfer clock  t
IICWHn = (
 When the normal mode
Transfer clock  f
IICWLn =
Transfer clock  t
IICWHn = (
 When the fast mode plus
Transfer clock  f
IICWLn =
Transfer clock  t
IICWHn = (
(2) Setting IICWLn and IICWHn registers on slave side
(The fractional parts of all setting values are truncated.)
 When the fast mode
IICWLn = 1.3
IICWHn = (1.2
 When the normal mode
IICWLn = 4.7
IICWHn = (5.3
 When the fast mode plus
IICWLn = 0.50
IICWHn = (0.50
(Caution and Remarks are listed on the next page.)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
f
CLK
IICWL0 + IICWH0 + f (t
CLK
0.52
CLK
0.48
 t )  f
R F
0.47
CLK
0.53
 t )  f
R F
0.50
CLK
0.50
 t )  f
R F

s  f
CLK

s  t  t )  f
R F CLK

s  f
CLK

s  t  t )  f
R F CLK

s  f
CLK

s  t  t )  f
R F CLK
CHAPTER 12 SERIAL INTERFACE IICA
+ t )
R F
CLK
CLK
CLK
485