Setting Overflow Time Of Watchdog Timer - Renesas RL78/G1P Hardware User Manual

RL78/G1P
Cautions 4. The operation of the watchdog timer in the HALT and STOP and SNOOZE modes differs as
follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
In HALT mode
In STOP mode
In SNOOZE mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.

8.4.2 Setting overflow time of watchdog timer

Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
counting again by writing "ACH" to the watchdog timer enable register (WDTE) during the window open period before the
overflow time.
The following overflow times can be set.
WDCS2
0
0
0
0
1
Remark f : Low-speed on-chip oscillator clock frequency
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R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
WDSTBYON = 0
Watchdog timer operation stops.
Table 8-3. Setting of Overflow Time of Watchdog Timer
WDCS1 WDCS0
0 0
0 1
1 0
1 1
0 0
Other than above
CHAPTER 8 WATCHDOG TIMER
Watchdog timer operation continues.
Overflow Time of Watchdog Timer
(f = 17.25 kHz (MAX.))
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6
2 /f (3.71 ms)
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7
2 /f (7.42 ms)
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8
2 /f (14.84 ms)
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9
2 /f (29.68 ms)
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11
2 /f (118.72 ms)
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Setting prohibited
WDSTBYON = 1
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