Snooze Mode Function - Renesas RL78/G1P Hardware User Manual

16-bit single-chip microcontroller
Hide thumbs Also See for RL78/G1P:
Table of Contents

Advertisement

RL78/G1P

9.8 SNOOZE Mode Function

In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D
conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed
without operating the CPU by inputting a hardware trigger. This is effective for reducing the operation current.
If the A/D conversion result range is specified using the ADUL and ADLL registers, A/D conversion results can be
judged at a certain interval of time in SNOOZE mode. Using this function enables power supply voltage monitoring and
input key judgment based on A/D inputs.
In the SNOOZE mode, only the following two conversion modes can be used:
 Hardware trigger wait mode (select mode, one-shot conversion mode)
 Hardware trigger wait mode (scan mode, one-shot conversion mode)
Caution The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for f
ELC
A/D conversion end
interrupt request
Note 1
signal
(INTAD)
When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP
mode. (For details about these settings, see 9.7.3 Setting up hardware trigger wait mode
STOP mode, bit 2 (AWC) of A/D converter mode register 2 (ADM2) is set to 1. After the initial settings are specified, bit 0
(ADCE) of A/D converter mode register 0 (ADM0) is set to 1.
If a hardware trigger is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to
the A/D converter. After supplying this clock, the system automatically counts up to the A/D power supply stabilization
wait time, and then A/D conversion starts.
The SNOOZE mode operation after A/D conversion ends differs depending on whether an interrupt signal is
generated
.
Note 1
Depending on the setting of the A/D conversion result comparison function (ADRCK bit, ADUL/ADLL
Notes 1.
register), there is a possibility of no interrupt signal being generated.
Be sure to set the ADM1 register to E1H.
2.
Remark The hardware trigger is event signal (any of INTP0 to INTP5) selected by ELC.
Specify the hardware trigger by using the A/D converter mode register 1 (ADM1).
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 9-34. Block Diagram When Using SNOOZE Mode Function
Hardware trigger
input
Clock request signal
(internal signal)
A/D converter
High-speed
on-chip oscillator clock
CHAPTER 9 A/D CONVERTER
Clock generator
.) Just before move to
Note 2
.
CLK
289

Advertisement

Table of Contents
loading

Table of Contents