Setting Up Test Mode - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.7.5 Setting up test mode

Start of setup
PER0 register setting
 ADM0 register setting
 ADM1 register setting
 ADM2 register setting
 ADUL/ADLL register setting
 ADS register setting
 ADTES register setting
(The order of the settings is
irrelevant.)
Reference voltage stabilization
wait time count A
ADCE bit setting
Reference voltage stabilization
wait time count B
ADCS bit setting
Start of A/D conversion
The A/D conversion operations are performed.
End of A/D conversion
Storage of conversion results in
the ADCR and ADCRH registers
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
Caution For the procedure for testing the A/D converter, see 20.10 A/D test function.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 9-33. Setting up Test Mode
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
 ADM0 register
FR2 to FR0, and LV0 bits:
ADMD bit: This is used to specify the select mode.
 ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: This is used to specify the one-shot conversion mode.
 ADM2 register
ADREFP1, ADREFP0, and ADREFM bits:
ADRCK bit: This is used to set the range for the A/D conversion result comparison
value generated by the interrupt signal to AREA2.
ADTYP bit: This is used to specify 12-bit resolution.
 ADUL/ADLL register
These set ADUL to FFH and ADLL to 00H (initial values).
 ADS register
ADS4, ADS2 to ADS0 bits: These are used to set to ANI0.
 ADTES register
ADTES1, ADTES0 bits: - side reference voltage/+ side reference voltage
The reference voltage stabilization wait time count A is required when the value of the
ADREFP1 and ADREFP0 bits is changed.
If change the ADREFP1 and ADREFP0 = 1, 0:
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: A = 1
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
If a test mode is selected (ADTES1 bit of ADTES register = 1) as the analog input

channel: B = 0.5 s
After counting up to the reference voltage stabilization wait time count B ends, the ADCS
bit of the ADM0 register is set (1), and A/D conversion starts.
The A/D conversion end interrupt (INTAD) is generated.
The conversion results are stored in the ADCR and ADCRH registers.
CHAPTER 9 A/D CONVERTER
These are used to specify the A/D conversion time.
These are used to select for the reference
voltage source.

A = 10

s
Note
s
288