Renesas RL78/G1P Hardware User Manual page 584

RL78/G1P
13.5.4 Holding DMA transfer pending by DWAITn bit
When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the
CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a
DMA transfer can be held pending by setting the DWAITn bit to 1. The DMA transfer for a transfer trigger that occurred
while DMA transfer was held pending is executed after the pending status is canceled. However, because only one
transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel during the
pending status, only one DMA transfer is executed after the pending status is canceled.
To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin, for example, the clock width
increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by setting the
DWAITn bit to 1.
After setting the DWAITn bit to 1, it takes two clocks until a DMA transfer is held pending.
Figure 13-10. Example of Setting for Holding DMA Transfer Pending by DWAITn Bit
Caution When DMA transfer is held pending while using two DMA channels, be sure to held the DMA
transfer pending for all channels (by setting DWAIT0 and DWAIT1 to 1). If the DMA transfer of one
channel is executed while that of the other channel is held pending, DMA transfer might not be
held pending for the latter channel.
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/f
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Starting DMA transfer
Main program
DWAITn = 1
Wait for 2 clocks
Wait for 9 clocks
DWAITn = 0
(f : CPU clock)
CLK CLK
CHAPTER 13 DMA CONTROLLER
P10 = 1
P10 = 0
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