Renesas RL78/G1P Hardware User Manual page 620

RL78/G1P
STOP Mode Setting
Item
System clock
Main system clock f
IH
f
X
f
EX
f
IL
CPU
Code flash memory
Data flash memory
RAM
Port (latch)
Timer array unit
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Serial array unit (SAU)
Serial interface (IICA)
DMA controller
Event link controller (ELC)
Power-on-reset function
Voltage detection function
External interrupt
CRC High-speed CRC
operation
General-purpose
function
CRC
RAM parity error detection
function
RAM guard function
SFR guard function
Illegal-memory access
detection function
(Remarks are listed on the next page.)
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware
for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart
the peripheral hardware.
2. To stop the low-speed on-chip oscillator clock in the STOP mode, must previously be set an option
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H =
0).
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the high-
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 16-2. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
High-speed On-chip Oscillator
Clock (f )
IH
Clock supply to the CPU is stopped
Stopped
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
Operation stopped
Operation stopped
Operation stopped
Status before STOP mode was set is retained
Operation disabled
See CHAPTER 8 WATCHDOG TIMER
Operation stopped
Wakeup operation is enabled (switching to the SNOOZE mode)
Operable (status before STOP mode was set is retained)
Wakeup operation is enabled only for CSIp and UARTq (switching to the SNOOZE mode)
Operation is disabled for anything other than CSIp and UARTq
Wakeup by address match operable
Operation disabled
Operable function blocks can be linked
Operable
Operation stopped
CHAPTER 16 STANDBY FUNCTION
When CPU Is Operating on
X1 Clock (f )
X
When CPU Is Operating on
External Main System Clock
(f )
EX
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