Renesas RL78/G1P Hardware User Manual page 754

16-bit single-chip microcontroller
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RL78/G1P
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
= 40 to +85C, 2.7 V  V
(T
A
Parameter
SCKp cycle time
Note 4
SCKp high-/low-level width
SIp setup time (to SCKp  )
Note 1
SIp hold time (from SCKp  )
Delay time from SCKp  to SOp output
SSI00 setup time
SSI00 hold time
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" and
the SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
"from SCKp↑" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. C is the load capacitance of the SOp output lines.
4. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Remarks 1.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
2.
f
: Serial array unit operation clock frequency
MCK
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
 3.6 V, V
= 0 V)
DD
SS
Symbol
t
KCY2
t
,
KH2
t
KL2
t
SIK2
Note 1
t
KSI2
Note 2
t
C = 30 pF
KSO2
t
DAPmn = 0
SSIK
DAPmn = 1
t
DAPmn = 0
KSSI
DAPmn = 1
CHAPTER 27 ELECTRICAL SPECIFICATIONS
Conditions
HS (high-speed main)
Mode
MIN.
16 MHz < f
8/f
MCK
MCK
 16 MHz
f
6/f
MCK
MCK
t
/2-8
KCY2
1/f
+20
MCK
1/f
+31
MCK
Note 3
120
1/f
+120
MCK
1/f
+120
MCK
120
LS (low-speed main)
Mode
MAX.
MIN.
MAX.
-
6/f
MCK
t
/2-8
KCY2
1/f
+30
MCK
1/f
+31
MCK
2/f
+44
2/f
MCK
MCK
120
1/f
+120
MCK
1/f
+120
MCK
120
Unit
ns
ns
ns
ns
ns
+110
ns
ns
ns
ns
ns
735

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