Renesas RL78/G1P Hardware User Manual page 249

RL78/G1P
Address: FFFA5H (CKS0), FFFA6H (CKS1)
Symbol <7>
CKSn PCLOEn
PCLOEn
0
1
CCSn2
0
0
0
0
1
1
1
1
Note Use the output clock within a range of 8 MHz. See 27.4 AC Characteristics for details.
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
2. To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0
before executing the STOP instruction.
Remarks 1. n = 0, 1
2. f : Main system clock frequency
MAIN
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 7-2. Format of Clock Output Select Register n (CKSn)
After reset: 00H
6 5
0 0
PCLBUZn pin output enable/disable specification
Output disable (default)
Output enable
CCSn1 CCSn0
0 0 f
MAIN
0 1 f /2
MAIN
1 0 f /2
MAIN
1 1 f /2
MAIN
0 0 f /2
MAIN
0 1 f /2
MAIN
1 0 f /2
MAIN
1 1 f /2
MAIN
R/W
4 3
0 0
PCLBUZn pin output clock selection
f = f
MAIN MAIN
5 MHz 10 MHz
5 MHz Setting
prohibited
2.5 MHz 5 MHz
2
1.25 MHz 2.5 MHz
3
625 kHz 1.25 MHz
4
312.5 kHz 625 kHz
11
2.44 kHz 4.88 kHz
12
1.22 kHz 2.44 kHz
13
610 Hz 1.22 kHz
2 1
CCSn2 CCSn1
= f = f
MAIN
20 MHz 32 MHz
Setting Setting
Note Note
prohibited prohibited
Setting Setting
Note
prohibited prohibited
5 MHz 8 MHz
2.5 MHz 4 MHz
1.25 MHz 2 MHz
9.76 kHz 15.63 kHz
4.88 kHz 7.81 kHz
2.44 kHz 3.91 kHz
0
CCSn0
=
MAIN
Note
Note
Note
230