Renesas RL78/G1P Hardware User Manual page 629

RL78/G1P
17.1 Timing of Reset Operation
This LSI is reset by input of the low level on the RESET
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the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the
operating clock starts.
High-speed on-chip
oscillator clock
High-speed system clock
(when X1 oscillation is selected)
CPU status
RESET pin
Internal reset signal
Port pin
Release from the reset state is automatic in the case of a reset due to a watchdog timer overflow, execution of an illegal
instruction, detection of a RAM parity error, or detection of illegal memory access. After reset processing, execution of the
program with the high-speed on-chip oscillator clock as the operating clock starts.
Figure 17-3. Timing of Reset Due to Execution of Illegal Instruction, Watchdog Timer Overflow, RAM Parity Error,
High-speed on-chip
oscillator clock
High-speed system clock
(when X1 oscillation is selected)
CPU status
Watchdog timer overflow/
Execution of illegal instruction/
Detection of RAM parity error/
Detection of illegal memory access
Internal reset signal
Port pin
(Notes, Caution, and Remark are listed on the next page.)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
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Figure 17-2. Timing of Reset by RESET Input
Normal operation
Delay
or Illegal Memory Access
Normal operation
CHAPTER 17 RESET FUNCTION
pin and released from the reset state by input of the high level on
Wait for oscillation accuracy stabilization
Reset period
Reset processing time when an external reset is released
Hi-Z
Wait for oscillation accuracy stabilization
Reset processing
Reset period
(oscillation stop)
0.0511 ms (TYP.)
0.0701 ms (MAX.)
Starting X1 oscillation is specified by software.
Normal operation
(high-speed on-chip oscillator clock)
Note 2
Starting X1 oscillation is specified by software.
Normal operation
(high-speed on-chip oscillator clock)
Note 2
Hi-Z
Note 1
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