Renesas RL78/G1P Hardware User Manual page 659

RL78/G1P
When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400

s or 5 clocks of f is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes,
IL
(0) clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the
LVIMD bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD.
Figure 19-8 shows the procedure for initial setting of interrupt and reset mode.
No
Remark f : Low-speed on-chip oscillator clock frequency
IL
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 19-8. Initial Setting of Interrupt and Reset Mode
Power supply started
Reset source
determined
LVIRF = 1?
Yes
LVISEN = 1
Voltage detection
stabilization wait time
LVIMD = 0
LVISEN = 0
Normal operation
CHAPTER 19 VOLTAGE DETECTOR
Refer to Figure 17-5 Procedure for Checking
Reset Source.
Check internal reset generation by LVD circuit
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)

Count 400 s or 5 clocks of f
Set the LVIMD bit to 0 to set interrupt mode.
Set the LVISEN bit to 0 to enable voltage detection.
by software.
IL
640