Renesas RL78/G1P Hardware User Manual page 554

16-bit single-chip microcontroller

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Table of Contents

(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)

(1) Start condition ~ address ~ data

(ACK detection)

(8 or 9 clock wait)

(ACK control)

(communication status)

(ST trigger)

(SP trigger)

(wait cancellation)

(transmit/receive)

(clock line)

(ACK detection)

(ST detection)

(SP detection)

(8 or 9 clock wait)

(ACK control)

(communication status)

(wait cancellation)

(transmit/receive)

Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master

2. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is

at least 4.0

3. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit.

Remark n = 0, 1

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

Figure 12-32. Example of Master to Slave Communication

Start condition

: Wait state by slave device

: Wait state by master and slave devices

s when specifying standard mode and at least 0.6

CHAPTER 12 SERIAL INTERFACE IICA

Slave address

s when specifying fast mode.