Renesas RL78/G1P Hardware User Manual page 722

RL78/G1P
Instruction Mnemonic
Group
8-bit data MOV A, [HL+B]
transfer
[HL+B], A
A, ES:[HL+B]
ES:[HL+B], A
A, [HL+C]
[HL+C], A
A, ES:[HL+C]
ES:[HL+C], A
X, !addr16
X, ES:!addr16
X, saddr
B, !addr16
B, ES:!addr16
B, saddr
C, !addr16
C, ES:!addr16
C, saddr
ES, saddr
XCH A, r
A, !addr16
A, ES:!addr16
A, saddr
A, sfr
A, [DE]
A, ES:[DE]
A, [HL]
A, ES:[HL]
A, [DE+byte]
A, ES:[DE+byte]
A, [HL+byte]
A, ES:[HL+byte]
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 26-5. Operation List (3/18)
Operands Bytes
Note 1 Note 2
2
2
3
3
2
2
3
3
3
4
2
3
4
2
3
4
2
3
Note 3
1 (r = X)
2 (other
than r =
X)
4
5
3
3
2
3
2
3
3
4
3
4
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the program memory area is accessed.
CLK
Clocks
A  (HL + B)
1 4
 (HL + B)  A
1
A  ((ES, HL) + B)
2 5
 ((ES, HL) + B)  A
2
A  (HL + C)
1 4
 (HL + C)  A
1
A  ((ES, HL) + C)
2 5
 ((ES, HL) + C)  A
2
X  (addr16)
1 4
X  (ES, addr16)
2 5
 X  (saddr)
1
B  (addr16)
1 4
B  (ES, addr16)
2 5
 B  (saddr)
1
C  (addr16)
1 4
C  (ES, addr16)
2 5
 C  (saddr)
1
 ES  (saddr)
1
 A  r
1
 A  (addr16)
2
 A  (ES, addr16)
3
 A  (saddr)
2
 A  sfr
2
 A  (DE)
2
 A  (ES, DE)
3
 A  (HL)
2
 A  (ES, HL)
3
 A  (DE + byte)
2
 A  ((ES, DE) + byte)
3
 A  (HL + byte)
2
 A  ((ES, HL) + byte)
3
CHAPTER 26 INSTRUCTION SET
Operation Flag
Z AC CY
703