Renesas RL78/G1P Hardware User Manual page 756

RL78/G1P
27.5.2 Serial interface IICA
= 40 to +85C, 2.7 V  V
(T
A
Parameter
SCLAn clock frequency
Setup time of restart condition
Note 1
Hold time
Hold time when SCLAn = "L"
Hold time when SCLAn = "H"
Data setup time (reception)
Data hold time (transmission)
Setup time of stop condition
Bus-free time
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
(acknowledge) timing.
Remarks 1. The maximum value of C
resistor) at that time in each mode are as follows.
Standard mode:
  Fast mode:
  Fast mode plus:
2. n = 0, 1
SCLA0/SCLA1
SDAA0/SDAA1
t
BUF
Stop
condition
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
 3.6 V, V
= 0 V)
DD SS
Symbol
Fast mode plus:
f
SCL
 10 MHz
f
CLK
Fast mode:
 3.5 MHz
f
CLK
Normal mode:
 1 MHz
f
CLK
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
Note 2
t
HD:DAT
t
SU:STO
t
BUF
HD:DAT
(communication line capacitance) and the value of R
b
C = 400 pF, R = 2.7 k
b b
C = 320 pF, R = 1.1 k
b b
C = 120 pF, R = 1.1 k
b b
IICA serial transfer timing
t t
LOW R
t
HD;DAT
t
HD;STA
Start
condition
CHAPTER 27 ELECTRICAL SPECIFICATIONS
Conditions Standard
MIN. MAX. MIN. MAX. MIN. MAX.
4.7
4.0
4.7
4.0
250
4.0
4.7
is during normal transfer and a wait state is inserted in the ACK
t t
HIGH F t
SU;STA
t
SU;DAT
Fast Mode
Mode
0 400
0 100
0.6 0.26
0.6 0.26
1.3
0.6 0.26
100
0 3.45 0 0.9
0.6 0.26
1.3
(communication line pull-up
b
t
HD;STA
Restart
condition
Fast Mode Unit
Plus
0 1000 kHz
kHz
kHz
 s
 s
 s
0.5
 s
50 ns
 s
0 0.45
 s
 s
0.5
t
SU;STO
Stop
condition
737