Cpu Clock Status Transition Diagram - Renesas RL78/G1P Hardware User Manual

RL78/G1P

5.6.3 CPU clock status transition diagram

Figure 5-14 shows the CPU clock status transition diagram of this product.
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Selectable by CPU
High-speed on-chip oscillator: Selectable by CPU
X1 oscillation/EXCLK input: Operating
(E)
oscillation/EXCLK
input → HALT
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 5-14. CPU Clock Status Transition Diagram
Power ON
(A)
Reset release
(B)
CPU: Operating
with high-speed
on-chip oscillator
(C)
CPU: Operating
with X1 oscillation or
EXCLK input
(G)
CPU: X1
CPU: X1
oscillation/EXCLK
input → STOP
CHAPTER 5 CLOCK GENERATOR
High-speed on-chip oscillator: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
V ≥ Lower limit of the operating voltage range
DD
(release from the reset state triggered by the LVD circuit or an external reset)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
(F)
CPU: High-speed
on-chip oscillator
→ STOP
(H)
CPU: High-speed
on-chip oscillator
(D)
→ SNOOZE
CPU: High-speed
on-chip oscillator
→ HALT
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Oscillatable
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
High-speed on-chip oscillator:
Operating
X1 oscillation/EXCLK input: Stops
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