Renesas RL78/G1P Hardware User Manual page 608

RL78/G1P
Example 1. Multiple interrupt servicing occurs twice
Main processing
INTxx
(PR = 11)
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt
servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable
interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than
that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is
acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with PR1 = 0, PR0 = 0 (higher priority level)
PR = 01: Specify level 1 with PR1 = 0, PR0 = 1
PR = 10: Specify level 2 with PR1 = 1, PR0 = 0
PR = 11: Specify level 3 with PR1 = 1, PR0 = 1 (lower priority level)
IE = 0: Interrupt request acknowledgment is disabled
IE = 1: Interrupt request acknowledgment is enabled.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 15-10. Examples of Multiple Interrupt Servicing (1/2)
INTxx servicing
IE = 0
EI
EI
INTyy
(PR = 10)
IE = 1 RETI
Main processing
EI IE = 0
INTxx INTyy
(PR = 10) (PR = 11)
IE = 1
1 instruction execution
CHAPTER 15 INTERRUPT FUNCTIONS
INTyy servicing
IE = 0 IE = 0
EI
INTzz
(PR = 01)
IE = 1
IE = 1 RETI
INTxx servicing INTyy servicing
EI
RETI
IE = 0
RETI
IE = 1
INTzz servicing
RETI
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