Renesas RL78/G1P Hardware User Manual page 564

RL78/G1P
(8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Address ~ data ~ data
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait)
ACKEn
H
(ACK control)
MSTSn
H
(communication status)
STTn
L
(ST trigger)
SPTn
L
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
L
(transmit/receive)
Bus line
SCLAn (bus)
(clock line)
SDAAn (bus)
ACK
R
(data line)
<3>
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
L
(SP detection)
WTIMn
H
(8 or 9 clock wait)
ACKEn
H
(ACK control)
MSTSn
L
(communication status)
WRELn
L
(wait cancellation)
INTIICAn
(interrupt)
TRCn
H
(transmit/receive)
Notes 1. For releasing wait state during reception of a master device, write "FFH" to IICAn or set the WRELn bit.
2. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a
slave device.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-33. Example of Slave to Master Communication
<5>
Note 1
<7>
<4>
D 7 D 6
1 1
Note 2
<6>
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
CHAPTER 12 SERIAL INTERFACE IICA
D 5 D 4 D 3 D 2 D
1 1 1 1 1
Note 1
<9>
<11>
<8>
ACK
1 D 0
1
<10>
<12>
Note 2
D 7
2
545