Renesas RL78/G1P Hardware User Manual page 599

RL78/G1P
15.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
The MK0L, MK0H, and MK1L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the MK0L
and MK0H registers are combined to form 16-bit registers MK0, they can be set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 15-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L)
Address: FFFE4H
Symbol <7>
MK0L PMK5
Address: FFFE5H
Symbol <7>
MK0H SREMK0
TMMK01H
Address: FFFE6H
Symbol <7>
MK1L TMMK03
XXMKX
0
1
Caution Be sure to set bits that are not available to the initial value.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
After reset: FFH R/W
<6> <5>
PMK4 PMK3
After reset: FFH R/W
<6> <5>
SRMK0 STMK0
CSIMK00
After reset: FFH R/W
<6> <5>
TMMK02 TMMK01
Interrupt servicing enabled
Interrupt servicing disabled
CHAPTER 15 INTERRUPT FUNCTIONS
<4> <3>
PMK2 PMK1
<4> <3>
DMAMK1 DMAMK0
<4> <3>
TMMK00 IICAMK1 TMMK03H
Interrupt servicing control
<2> <1> <0>
PMK0 LVIMK WDTIMK
<2> <1> <0>
FLMK IICAMK0 ADMK
<2> 1
1
0
1
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