Renesas RL78/G1P Hardware User Manual page 229

RL78/G1P
Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (2/2)
Operation Sets the TOEmp bit (slave) to 1 (only when operation is
start resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
Count operation of the master channel is started by start
trigger detection of the master channel.
 Detects the TImn pin input valid edge.
 Sets the TSmn bit of the master channel to 1 by
software
During Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
operation
Set values of the TMRmp, TDRmn, TDRmp registers,
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers by slave
channel can be changed.
Operation The TTmn (master) and TTmp (slave) bits are set to 1 at
stop the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
The TOEmp bit of slave channel is cleared to 0 and
value is set to the TOmp bit.
TAU To hold the TOmp pin output level
stop Clears the TOmp bit to 0 after the value to
be held is set to the port register.
When holding the TOmp pin output level is not
necessary
Setting not required.
The TAUmEN bit of the PER0 register is cleared to 0.
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
The TEmn and TEmp bits are set to 1 and the master
channel enters the start trigger detection (the valid edge of
the TImn pin input is detected or the TSmn bit of the
master channel is set to 1) wait status.
Counter stops operating.
Master channel starts counting.
Master channel loads the value of the TDRmn register to
timer count register mn (TCRmn) when the TImn pin valid
input edge is detected, and the counter starts counting
down. When the count value reaches TCRmn = 0000H,
the INTTMmn output is generated, and the counter stops
until the next valid edge is input to the TImn pin.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of the TDRmp register to the
TCRmp register, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of INTTMmn from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp = 0, and count operation stops.
The TCRmn and TCRmp registers hold count value and
stop.
The TOmp output is not initialized but holds current
status.
The TOmp pin outputs the TOmp set level.
The TOmp pin output level is held by port function.
Input clock supply for timer array unit 0 is stopped.
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
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