Renesas RL78/G1P Hardware User Manual page 650

RL78/G1P
19.4 Operation of Voltage Detector
19.4.1 When used as reset mode
 When starting operation
Start in the following initial setting state.
Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V
using the option byte 000C1H.
 Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS))
When the option byte LVIMDS1 and LVIMDS0 are set to 1, the initial value of the LVIS register is set to 81H.

Bit 7 (LVIMD) is 1 (reset mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: V
 Operation in LVD reset mode
In the reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1), the state of an internal reset by LVD is retained until
the supply voltage (V
released when the supply voltage (V
At the fall of the operating voltage, an internal reset by LVD is generated when the supply voltage (V
below the voltage detection level (V
Figure 19-4 shows the timing of the internal reset signal generated by the voltage detector.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
) exceeds the voltage detection level (V
DD
) exceeds the voltage detection level (V
DD
).
LVD
CHAPTER 19 VOLTAGE DETECTOR
V ).
LVDL or LVD
) after power is supplied. The internal reset is
LVD
).
LVD
) falls
DD
) by
LVD
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