Renesas RL78/G1P Hardware User Manual page 186

RL78/G1P
(4) Operation of one-count mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and
count starts.
<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of
the TCRmn register becomes FFFFH and counting stops.
f
MCK
(f )
TCLK
TSmn (write)
TEmn
TImn input
Rising edge
Start trigger
detection signal
TCRmn
INTTMmn
Remark The above figure shows the timing when the noise filter is not in use. By making the noise filter on-state,
the edge detection becomes 2 f
TImn input. The error per one period occurs be the asynchronous between the period of the TImn input
and that of the count clock (f
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 6-28. Operation Timing (In One-count Mode)
<1>
<3>
Edge detection
<2>
Initial value
Start trigger input wait status
cycles (it sums up to 3 to 4 cycles) later than the normal cycle of
MCK
).
MCK
CHAPTER 6 TIMER ARRAY UNIT
<4>
m
<5>
0
FFFF
1
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