Renesas RL78/G1P Hardware User Manual page 243

RL78/G1P
Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
TAU
default
setting
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel Sets timer mode registers mn, mp, 0q (TMRmn, TMRmp,
default TMRmq) of each channel to be used (determines
setting operation mode of channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp and TDRmq registers of the slave
channels.
Sets slave channels.
The TOMmp and TOMmq bits of timer output mode
register m (TOMm) are set to 1 (slave channel output
mode).
Sets the TOLmp and TOLmq bits.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
Sets the TOEmp and TOEmq bits to 1 and enables
operation of TOmp and TOmq.
Clears the port register and port mode register to 0.
(Remark is listed on the next page.)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
Input clock supply for timer array unit 0 is stopped.
(Clock supply is stopped and writing to each register is
disabled.)
Input clock supply for timer array unit 0 is supplied. Each
channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOmp and TOmq pins go into Hi-Z output state.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
TOmp and TOmq do not change because channels stop
operating.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
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