Renesas RL78/G1P Hardware User Manual page 631

RL78/G1P
Item
System clock
Main system clock
f
IL
CPU
Code flash memory
Data flash memory
RAM
Port (latch)
Timer array unit
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Serial array unit (SAU)
Serial interface (IICA)
DMA controller
Event link controller (ELC)
PWM option unit
Power-on-reset function
Voltage detection function
External interrupt
High-speed CRC
CRC
operation General-purpose CRC
function
RAM parity error detection function
RAM guard function
SFR guard function
Illegal-memory access detection
function
Remark f : High-speed on-chip oscillator clock
IH
f : X1 oscillation clock
X
f : External main system clock
EX
f : Low-speed on-chip oscillator clock
IL
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 17-1. Operation Statuses During Reset Period
Clock supply to the CPU is stopped.
f Operation stopped
IH
f Operation stopped (the X1 and X2 pins are input port mode)
X
f Clock input invalid (the pin is input port mode)
EX
Operation stopped
Operation stopped
Operation stopped
Operation stopped
P40 becomes high impedance (external reset or POR reset).
P40 is pulled-up (resets other than external reset and POR reset).
The port pins except for P40 become high impedance.
Operation stopped
Detection operation possible
Operation is possible in the case of an LVD reset and stopped in the case of other types of
reset.
Operation stopped
CHAPTER 17 RESET FUNCTION
During Reset Period
612