Renesas RL78/G1P Hardware User Manual page 616

RL78/G1P
HALT Mode Setting
Item
System clock
Main system clock f
IH
f
X
f
EX
f
IL
CPU
Code flash memory
Data flash memory
RAM
Port (latch)
Timer array unit
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Serial array unit (SAU)
Serial interface (IICA)
DMA controller
Event link controller (ELC)
Power-on-reset function
Voltage detection function
External interrupt
CRC High-speed CRC
operation
General-purpose
function
CRC
RAM parity error detection
function
RAM guard function
SFR guard function
Illegal-memory access
detection function
Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f : High-speed on-chip oscillator clock
IH
f : Low-speed on-chip oscillator clock
IL
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 16-1. Operating Statuses in HALT Mode
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
High-speed On-chip Oscillator
Clock (f )
IH
Clock supply to the CPU is stopped
Operation continues (cannot
be stopped)
Operation disabled
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
Operation stopped
Operation stopped
Status before HALT mode was set is retained
Operable
See CHAPTER 8 WATCHDOG TIMER
Operable
Operable function blocks can be linked
Operable
In the calculation of the RAM area, operable when DMA is executed only
Operable when DMA is executed only
f
EX
f
X
CHAPTER 16 STANDBY FUNCTION
When CPU Is Operating on
X1 Clock (f )
X
Operation disabled
Operation continues (cannot
be stopped)
Cannot operate
: External main system clock
: X1 clock
When CPU Is Operating on
External Main System Clock
(f )
EX
Cannot operate
Operation continues (cannot
be stopped)
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