Renesas RL78/G1P Hardware User Manual page 623

RL78/G1P
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
(2) When high-speed on-chip oscillator clock is used as CPU clock
Reset signal
Status of CPU
High-speed on-chip
oscillator clock
Note For the reset processing time, see CHAPTER 17 RESET FUNCTION.
For the reset processing time of the power-on-reset circuit (POR) and voltage detector (LVD), see
CHAPTER 18 POWER-ON-RESET CIRCUIT.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 16-6. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Normal operation
(high-speed
system clock) STOP mode
Oscillation stopped
Oscillates
STOP
instruction
Normal operation
(high-speed on-chip
oscillator clock) STOP mode
Oscillation stopped
Oscillates
CHAPTER 16 STANDBY FUNCTION
Normal operation
Reset (high-speed on-chip
Note
period oscillator clock)
Oscillation Oscillation
stopped stopped
Oscillates
Oscillation stabilization time
(Check by using OSTC register)
Starting X1 oscillation is
specified by software.
Normal operation
Reset (high-speed on-chip
Note
period oscillator clock)
Oscillation
stopped
Oscillates
Wait for oscillation
accuracy stabilization
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