Renesas RL78/G1P Hardware User Manual page 634

RL78/G1P
Reset function
Voltage detector (LVD)
DMA controller
ELC
Interrupt
Safety functions
Flash memory
BCD correction circuit
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2. These values vary depending on the reset source.
Reset Source RESET Input
Register
RESF TRAP bit Cleared (0)
WDTRF bit
RPERF bit
IAWRF bit
LVIRF bit
LVIM LVISEN bit Cleared (0)
LVIOMSK bit Held
LVIF bit
LVIS
3. The generation of reset signal other than an LVD reset sets as follows.
 When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
 When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
 When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 17-2. Hardware Statuses After Reset Acknowledgment (3/3)
Hardware
Reset control flag register (RESF)
Voltage detection register (LVIM)
Voltage detection level register (LVIS)
SFR address registers 0, 1 (DSA0, DSA1)
RAM address registers 0, 1 (DRA0, DRA1)
Byte count registers 0, 1 (DBC0, DBC1)
Mode control registers 0, 1 (DMC0, DMC1)
Operation control registers 0, 1 (DRC0, DRC1)
Event output select registers 00 to 09 (ELSELR00 to ELSELR09)
Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L)
Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L)
Priority specification flag registers 00L, 00H, 01L, 10L, 10H, 11L (PR00L,
PR00H, PR01L, PR10L, PR10H, PR11L)
External interrupt rising edge enable register 0 (EGP0)
External interrupt falling edge enable register 0 (EGN0)
Flash memory CRC control register (CRC0CTL)
Flash memory CRC operation result register (PGCRCL)
CRC input register (CCRIN)
CRC data register (CRCD)
Invalid memory access detection control register (IAWCTL)
RAM parity error control register (RPECTL)
Data flash control register (DFLCTL)
BCD correction result register (BCDAJ)
Reset by
POR
Illegal Instruction
Reset by Reset by
Execution of WDT
Set (1) Held
Held Set (1)
Held
Held
Held
Cleared (00H/01H/81H)
CHAPTER 17 RESET FUNCTION
Status After Reset
Acknowledgment
Undefined
Note 2
00H
00H/01H/81H
00H
0000H
0000H
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
0000H
00H
0000H
00H
00H
00H
Undefined
Reset by RAM Reset by
Parity Error Illegal-memory
Access
Held
Set (1) Held
Set (1)
Note 1
Note 2
Notes 2, 3
Reset by
LVD
Held
Set (1)
Held
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