Renesas RL78/G1P Hardware User Manual page 657

RL78/G1P
Figure 19-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
Supply voltage (V )
DD
V
LVDH
V
LVDL
Lower limit of operation voltage
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
LVIMK flag
(set by software)
Operation status
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
LVILV flag
LVIRF flag
LVD reset signal
POR reset signal
Internal reset
signal
INTLVI
LVIIF flag
(Notes and Remark are listed on the next page.)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
When a condition of V is V < V
DD DD
a reset is generated because of LVIMD = 1 (reset mode).
Note 1
H
Cleared by
software
Normal
Save
RESET
operation processing
Cleared by
Note 2
software
CHAPTER 19 VOLTAGE DETECTOR
after releasing the mask,
LVDH
Wait for stabilization by software (400 μs or 5 clocks of f
RESET
processing
Cleared by
software
Time
Cleared by software
Normal
RESET
operation
Save
Cleared
Note 3
Cleared
Note 3
)
IL
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