Renesas RL78/G1P Hardware User Manual page 469

RL78/G1P
Wait for receive completes
Transfer end interrupt
Reading receive data from the SDRmn
[7:0] bits (RXDq register) (8 bits) or
the SDRmn [8:0] bits (9 bits)
Indicating normal reception?
No
Reception completed?
Writing 1 to the STmn bit
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 11-113. Flowchart of UART Reception
Starting UART
communication
SAU default setting
Setting receive data
Enables interrupt
Yes
RETI
Yes
Interrupt (mask)
End of UART
CHAPTER 11 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 11-109.
(setting to mask for error interrupt)
Setting storage area of the receive data
(storage area, reception data pointer, and number of communication data are
optionally set on the internal RAM by the software).
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and set.
Starting reception if start bit is detected.
When receive complete, transfer end interrupt is generated.
Read receive data then writes to storage area.
Update receive data pointer and number of
communication data.
No
Error processing
Check the number of communication data, determine the
completion of reception
, number of communication data
450