Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode)

<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D
conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
conversion of the channel following the specified channel automatically starts.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not stop in this status.
<9> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Note If a high-accuracy channel is selected as the analog input channel: Stabilization wait time = 0.5
If a standard channel is selected as the analog input channel:
Figure 9-23. Example of Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
<1> ADCE is set to 1.
ADCE
<2> ADCS is set to 1.
A hardware trigger
<3>
is generated.
Hardware
trigger
Trigger
The trigger is not
standby
acknowledged.
status
ADCS
ADS
ANI0 to ANI3
A/D
Stop Conversion Data 1 Data 2
conversion
status standby (ANI0) (ANI1)
status
ADCR,
Data 1
ADCRH
(ANI0)
INTAD
The interrupt is generated four times.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Operation Timing
A hardware trigger is
<5>
generated during A/D
conversion operation.
A/D conversion Conversion is
<4>
ends and the next interrupted
conversion starts. and restarts.
Data 3 Data 4 Data 5 Data 7 Data 8 Data 9
Data 6
(ANI2) (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2)
Data 2 Data 3 Data 4 Data 5 Data 7 Data 8
(ANI1) (ANI2) (ANI3) (ANI0) (ANI0) (ANI1)
The interrupt is generated four times.
Note , the ADCS bit of the ADM0 register is set to 1 to
After A/D conversion of the four channels ends, the A/D
Stabilization wait time = 2
<6> ADS is rewritten during
A/D conversion operation.
ANI4 to ANI7
Conversion is
<4>
interrupted
and restarts.
Data 10 Data 13 Data 14 Data 15 Data 16
Data 11
Data 12
(ANI3) (ANI0) (ANI1) (ANI4) (ANI5) (ANI6)
(ANI7)
Data 9 Data 11 Data 13 Data 14 Data 15
Data 10
(ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6)
The interrupt is generated four times.
CHAPTER 9 A/D CONVERTER

s
ADCE is cleared to 0. <9>
ADCS is overwritten <7> ADCS is cleared to 0
with 1 during A/D during A/D conversion
conversion operation. operation.
Conversion is
<4>
interrupted
and restarts.
Data 17 Data 18 Data Data 20 Data 21 Data 22 Data 23
19
(ANI4) (ANI5) (ANI4) (ANI5) (ANI6) (ANI7)
(ANI6)
Data 16 Data 17 Data 18 Data 20 Data 21 Data 22
(ANI7) (ANI4) (ANI5) (ANI4) (ANI5) (ANI6)
The interrupt is generated four times.

s
The trigger is not
acknowledged.
<8>
Conversion is
<4>
interrupted.
Data 24 Stop
Conversion
(ANI4) standby status
Data 23
(ANI7)
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