Renesas RL78/G1P Hardware User Manual page 594

RL78/G1P
Interrupt
Type
Name
Maskable 0 INTWDTI
1 INTLVI
2 INTP0
3 INTP1
4 INTP2
5 INTP3
6 INTP4
7 INTP5
8 INTAD
9 INTIICA0
10 INTFL
11 INTDMA0
12 INTDMA1
13 INTST0/
INTCSI00
14 INTSR0
15 INTSRE0
INTTM01H
16 INTTM03H
17 INTIICA1
18 INTTM00
19 INTTM01
20 INTTM02
21 INTTM03
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 21 indicates the lowest priority.
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 15-1.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 15-1. Interrupt Source List (1/2)
Interrupt Source
Trigger
Note 3
Watchdog timer interval
(75% of overflow time+1/2f )
IL
Note 4
Voltage detection
Pin input edge detection
End of A/D conversion
End of IICA0 communication
Reserved
End of DMA0 transfer
End of DMA1 transfer
UART0 transmission transfer end or buffer empty
interrupt/CSI00 transfer end or buffer empty interrupt
UART0 reception transfer end
UART0 reception communication error occurrence
End of timer channel 01 count or capture (at higher 8-bit timer
operation)
End of timer channel 03 count or capture (at higher 8-bit timer
operation)
End of IICA1 communication
End of timer channel 00 count or capture
End of timer channel 01 count or capture (at 16-bit/lower 8-bit
timer operation)
End of timer channel 02 count or capture
End of timer channel 03 count or capture (at 16-bit/lower 8-bit
timer operation)
CHAPTER 15 INTERRUPT FUNCTIONS
Internal/
External
Internal
External
Internal
Vector
Table
Address
(A)
00004H
00006H
(B)
00008H
0000AH
0000CH
0000EH
00010H
00012H
(A)
00014H
00016H
00018H
0001AH
0001CH
0001EH
00020H
00022H
00028H
0002AH
0002CH
0002EH
00030H
00032H
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