Renesas RL78/G1P Hardware User Manual page 344

RL78/G1P
Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01)
Symbol 15 14
SSRmn 0 0
FEFm
Note
n
0 No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
 1 is written to the FECTmn bit of the SIRmn register.
<Set condition>
 A stop bit is not detected when UART reception ends.
PEF
mn
0 No error occurs.
1 Parity error occurs (during UART reception) or ACK is not detected (during I
<Clear condition>
 1 is written to the PECTmn bit of the SIRmn register.
<Set condition>
 The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
OVF
mn
0 No error occurs.
1 An error occurs
<Clear condition>
 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
 Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next
receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and
reception mode in each communication mode).
 Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
Note The SSR01 register only.
Caution When the CSI is performing reception operations in the SNOOZE mode (SWCm = 1), the OVFmn flag
will not change.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 11-9. Format of Serial Status Register mn (SSRmn) (2/2)
13 12 11 10
0 0 0 0
Framing error detection flag of channel n
Parity/ACK error detection flag of channel n
Overrun error detection flag of channel n
CHAPTER 11 SERIAL ARRAY UNIT
After reset: 0000H R
9 8 7 6
0 0 0 TSF BFF
mn mn
5 4 3 2
0 0 FEFm PEF
Note
n
2
C transmission).
1 0
OVF
mn mn
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