Renesas RL78/G1P Hardware User Manual page 76

RL78/G1P
ES: [HL + byte], ES: [DE + byte]
<1> <2>
Instruction code
OP-code
byte
<3>
The ES register <1> specifies a 64-Kbyte area within the
overall 1 MB space as the four higher-order bits, X, of
the address range.
Either pair of registers <2> specifies the address
where the target array of data starts in the 64-Kbyte
area specified in the ES register <1>.
"byte" <3> specifies an offset within the array to the
target location in memory.
ES: word [B], ES: word [C]
<1> <2>
Instruction code
OP-code
Low Addr.
<2>
High Addr.
The ES register <1> specifies a 64-Kbyte area within the overall
1-Mbyte space as the four higher-order bits, X, of the address range.
"word" <2> specifies the address where the target array of word-sized data
starts in the 64-Kbyte area specified in the ES register <1>.
Either register <3> specifies an off set within the array to the target location
in memory.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 3-27. Example of ES:[HL+byte], ES:[DE+byte]
<3> <1> <2> <3>
<2>
rp(HL/DE)
<1>
ES
Figure 3-28. Example of ES:word[B], ES:word[C]
<3> <1> <2> <3>
<3>
<2>
Address of a word within an array
<1>
ES
<3>
Offset
<2> Address of
an array
X0000H
Specifies a
<1>
64 KB area
<3>
Offset
r(B/C)
X0000H
Specifies a
<1>
64 KB area
CHAPTER 3 CPU ARCHITECTURE
XFFFFH
Target memory
Other data in
the array
X0000H
Memory
XFFFFH
Target memory
X0000H
Memory
Target
array
of data
Array of
word-sized
data
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