Renesas RL78/G1P Hardware User Manual page 748

RL78/G1P
27.4 AC Characteristics
= 40 to +85C, 2.7 V  V
(T
A
Items
Instruction cycle (minimum
instruction execution time)
External system clock
frequency
External system clock input
high-level width, low-level width
TI00 to TI03 input high-level
width, low-level width
TO00 to TO03 output frequency f
PCLBUZ0, PCLBUZ1 output
frequency
Interrupt input high-level width,
low-level width
RESET low-level width
Remark f : Timer array unit operation clock frequency
MCK
(Operation clock to be set by the CKSmn0 and CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0), n: Channel number (n = 0 to 3))
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
 3.6 V, V
= 0 V)
DD SS
Symbol
T Main system clock
CY
(f ) operation
MAIN
In the self-
programming mode
f
EX
t ,
EXH
t
EXL
t ,
TIH
t
TIL
HS (high-speed main) mode
TO
LS (low-speed main) mode
f HS (high-speed main) mode
PCL
LS (low-speed main) mode
t , INTP0 to INTP5
INTH
t
INTL
t
RSL
CHAPTER 27 ELECTRICAL SPECIFICATIONS
Conditions
HS (high-speed main) mode
LS (low-speed main) mode
HS (high-speed main) mode
LS (low-speed main) mode
MIN. TYP. MAX.
0.03125 1
0.125 1
0.03125 1
0.125 1
1.0 20.0
24
1/f +10
MCK
8
4
8
4
1
10
Unit

s

s

s

s
MHz
ns
ns
MHz
MHz
MHz
MHz

s

s
729