Renesas RL78/G1P Hardware User Manual page 638

RL78/G1P
18.1 Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the following functions.
 Generates internal reset signal at power on.
The reset is released when the supply voltage (V
status using the voltage detection function or external reset pin until the voltage reaches the operating voltage range
shown in 27.4 AC Characteristics.
 Compares supply voltage (V
However, when the operating voltage falls, enter STOP mode, or enable the reset status using the voltage detection
function or external reset pin before the voltage falls below the operating voltage range shown in 27.4 AC
Characteristics. When restarting operation, confirm that the supply voltage has returned to the operating voltage
range.
Caution If an internal reset signal is generated in the POR circuit, TRAP, WDTRF, RPERF, IAWRF, and LVIRF
flags of the reset control flag register (RESF) is cleared.
Remarks 1. This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset source is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution,
RAM parity error, or illegal-memory access. The RESF register is not cleared to 00H and the flag is set
to 1 when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD),
illegal instruction execution, RAM parity error, or illegal-memory access. For details of the RESF register,
see CHAPTER 17 RESET FUNCTION.
ADPC: A/D port configuration register
2. V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
For details, see 27.6.4 POR circuit characteristics.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 18 POWER-ON-RESET CIRCUIT
) exceeds the detection voltage (V
DD
) and detection voltage (V
DD
CHAPTER 18 POWER-ON-RESET CIRCUIT
), generates internal reset signal when V
PDR
). However, keep the reset
POR
< V
DD
.
PDR
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