Renesas RL78/G1P Hardware User Manual page 652

RL78/G1P
19.4.2 When used as interrupt mode
 When starting operation
Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (V
using the option byte 000C1H.
Start in the following initial setting state.
Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level

register (LVIS))
 When the option byte LVIMDS1 is clear to 0 and LVIMDS0 is set to 1, the initial value of the LVIS register is
set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: V
 Operation in LVD interrupt mode
In the interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1), the state of an internal reset by LVD is retained
until the supply voltage (V
release of the POR). The internal reset is released when the supply voltage (V
level (V ).
LVD
An interrupt request signal by LVD (INTLVI) is generated, when the supply voltage (V
detection level (V
release of the POR. When the voltage falls, this LSI should be placed in the STOP mode, or placed in the reset
state by controlling the externally input reset signal, before the voltage falls below the operating voltage range
defined in 27.4 AC Characteristics. When restarting the operation, make sure that the operation voltage has
returned within the range of operation.
Figure 19-5 shows the timing of the internal interrupt signal generated by the voltage detector.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
) exceeds the voltage detection level (V
DD
) or when the supply voltage (V
LVD
CHAPTER 19 VOLTAGE DETECTOR
or V ).
LVDL LVD
) after power is supplied (after the first
LVD
) exceeds the voltage detection level (V
DD
) exceeds the voltage detection
DD
) falls below the voltage
DD
) after the second
LVD
) by
LVD
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