A/D Converter Mode Register 2 (Adm2) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.3.4 A/D converter mode register 2 (ADM2)

This register is used to select the + side or - side reference voltage of the A/D converter, check the upper limit and
lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode.
The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F0010H After reset: 00H
Symbol 7
ADM2 ADREFP1
ADREFP1
0
0
1
1
 When ADREFP1 or ADREFP0 bit is rewritten, this must be configured in accordance with the following procedures.
(1) Set ADCE = 0
(2) Change the values of ADREFP1 and ADREFP0
(3) Reference voltage stabilization wait time (A)
(4) Set ADCE = 1
(5) Reference voltage stabilization wait time (B)
The stabilization wait time indicated by (3) is required when the value of the ADREFP1 and ADREFP0 bits is
changed.
When ADREFP1 and ADREFP0 are changed to 1 and 0:
When ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1:
The stabilization wait time indicated by (5) is required when the value of the ADCE bit is changed to 1.
If a high-accuracy channel is selected as the analog input channel:
If a test mode setting (ADTES1 bit of ADTES register = 1) is selected: 0.5
If a standard channel is selected as the analog input channel:
If a temperature sensor output/internal reference voltage output are selected as the analog input channel: (ADISS bit
of ADS register = 1):
After (5) stabilization time, start the A/D conversion.
 When ADREFP1 and ADREFP0 are set to 1 and 0, respectively, A/D conversion cannot be performed on the
temperature sensor output and internal reference voltage output.
Be sure to perform A/D conversion while ADISS = 0.
Note This setting can be used only in HS (high-speed main) mode. For detail, refer to Figure 22-3 Format of User
Option Byte (000C2H).
Cautions 1. Only rewrite the value of the ADM2 register while conversion is stopped (ADCS = 0, ADCE = 0).
2. Do not set the ADREFP1 bit to 1 when shifting to STOP mode. Also, if the ADREFP1 bit is set to
1, the A/D converter reference voltage current (I
characteristics will be added to the current consumption when shifting to HALT mode while the
CPU is operating on the main system clock.
3. When using AV
input mode by using the port mode register.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 9-7. Format of A/D Converter Mode Register 2 (ADM2) (1/2)
R/W
6 5
ADREFP0 ADREFM
ADREFP0 Selection of the + side reference voltage source of the A/D converter
0 Supplied from V
1 Supplied from P20/AV
0 Supplied from the internal reference voltage (1.45 V)
1 Setting prohibited
and AV
REFP REFM
4 <3>
0 ADRCK
DD
/ANI0
REFP
ADREF
, specify ANI0 and ANI1 as the analog input channels and specify
CHAPTER 9 A/D CONVERTER
<2> 1
AWC 0
Note
 s
A = 10
 s
A = 1
 s
0.5
 s
 s
2
 s
2
) indicated in 27.3.2
<0>
ADTYP
Supply current
258