Renesas RL78/G1P Hardware User Manual page 601

RL78/G1P
15.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0)
These registers specify the valid edge for INTP0 to INTP5.
The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 15-5. Format of External Interrupt Rising Edge Enable Register (EGP0) and
Address: FFF38H After reset: 00H
Symbol 7
EGP0 0
Address: FFF39H After reset: 00H
Symbol 7
EGN0 0
EGPn
0
0
1
1
Table 15-3 shows the ports corresponding to the EGPn and EGNn bits.
Caution When the input port pins used for the external interrupt functions are switched to the output mode,
the INTPn interrupt might be generated upon detection of a valid edge.
When switching the input port pins to the output mode, set the port mode register (PMxx) to 0 after
disabling the edge detection (by setting EGPn and EGNn to 0).
Remarks 1. For details on the edge detection ports, see 2.1 Pin Function List.
2. n = 0 to 5
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
External Interrupt Falling Edge Enable Register (EGN0)
R/W
6 5
0 EGP5 EGP4
R/W
6 5
0 EGN5 EGN4
EGNn
0 Edge detection disabled
1 Falling edge
0 Rising edge
1 Both rising and falling edges
Table 15-3. Ports Corresponding to EGPn and EGNn bits
Detection Enable Bit
EGP0 EGN0
EGP1 EGN1
EGP2 EGN2
EGP3 EGN3
EGP4 EGN4
EGP5 EGN5
CHAPTER 15 INTERRUPT FUNCTIONS
4 3 2
EGP3 EGP2
4 3 2
EGN3 EGN2
INTPn pin valid edge selection (n = 0 to 5)
Interrupt Request Signal
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
1 0
EGP1 EGP0
1 0
EGN1 EGN0
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