Renesas RL78/G1P Hardware User Manual page 696

RL78/G1P
An overview of the data flash memory is provided below. For details of a method for rewriting the data flash memory,
refer to the RL78 Family Data Flash Library User's Manual.
 The data flash memory can be written to by using the flash memory programmer or an external device
 Programming is performed in 8-bit units
 Blocks can be deleted in 1 KB units
 The only access by CPU instructions is byte reading (1 clock cycle + wait 3 clock cycles)
 Because the data flash memory is an area exclusively used for data, it cannot be used to execute instructions (code
fetching)
 Instructions can be executed from the code flash memory while rewriting the data flash memory (That is, back ground
operation (BGO) is supported)
 Accessing the data flash memory is not possible while rewriting the code flash memory (during self-programming)
 Because the data flash memory is stopped after a reset ends, the data flash control register (DFLCTL) must be set
up in order to use the data flash memory
 Manipulating the DFLCTL register is not possible while rewriting the data flash memory
 Transition the HALT/STOP status is not possible while rewriting the data flash memory
Caution The high-speed on-chip oscillator should be kept operating during data flash rewrite. If it is kept
stopping, it should be operated (HIOSTOP = 0). The data flash library should be executed after 30
have elapsed.
Remark For the flash programming mode, see 23.7 Flash Memory Programming by Self-programming.
23.4.2 Register controlling data flash memory
23.4.2.1 Data flash control register (DFLCTL)
This register is used to enable or disable accessing to the data flash.
The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Address: F0090H After reset: 00H
Symbol 7
DFLCTL 0
DFLEN
0
1
Caution Manipulating the DFLCTL register is not possible while rewriting the data flash memory.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 23-6. Format of Data Flash Control Register (DFLCTL)
R/W
6 5
0 0
Disables data flash access
Enables data flash access
CHAPTER 23 FLASH MEMORY
4 3
0 0
Data flash access control
2 1 <0>
0 0 DFLEN
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