Serial Channel Enable Status Register M (Sem) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.3.10 Serial channel enable status register m (SEm)

The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped.
When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1
is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of the CKOmn bit (serial clock output of
channel n) of serial output register m (SOm) to be described below, and a value reflected by a communication operation is
output from the serial clock pin.
Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its value
from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be created by
software.
The SEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SEmL.
Reset signal generation clears the SEm register to 0000H.
Figure 11-12. Format of Serial Channel Enable Status Register m (SEm)
Address: F0120H, F0121H (SE0)
Symbol 15 14
SE0 0 0
SEm
n
0 Operation stops
1 Operation is enabled.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
After reset: 0000H R
13 12 11 10
0 0 0 0
Indication of operation enable/stop status of channel n
CHAPTER 11 SERIAL ARRAY UNIT
9 8 7 6
0 0 0 0
5 4 3 2
0 0 0 0 SE01 SE00
1 0
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