Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
Page 3 Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 4 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The RL78/G1P manual is separated into two parts: this manual and the software edition (common to the RL78 Family). RL78/G1P RL78 Family User’s Manual...
Page 5 E2 Emulator User’s Manual R20UT3538E E2 Lite Emulator User’s Manual R20UT3240E Renesas Flash Programmer Flash Memory Programming Software User’s Manual R20UT4066E Renesas Flash Development Toolkit User’s Manual R20UT0508E Caution The related documents listed above are subject to change without notice. Be sure to use the latest...
Page 6 All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
Page 7: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE..........................1 1.1 Features ............................1 1.2 List of Part Numbers ........................3 1.3 Pin Configuration (Top View) ......................4 1.3.1 24-pin products ........................... 4 1.3.2 32-pin products ........................... 5 1.4 Pin Identification ..........................6 1.5 Block Diagram ..........................7 1.5.1 24-pin products ...........................
Page 8 3.1.4 Special function register (SFR) area ....................33 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ......33 3.1.6 Data memory addressing ......................... 34 3.2 Processor Registers ........................35 3.2.1 Control registers ..........................35 3.2.2 General-purpose registers ........................ 37 3.2.3 ES and CS registers .........................
Page 9 4.4 Port Function Operations ......................90 4.4.1 Writing to I/O port ..........................90 4.4.2 Reading from I/O port ........................90 4.4.3 Operations on I/O port ........................90 4.5 Settings of Port Related Register When Using Alternate Function ........91 4.6 Cautions When Using Port Function ..................94 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) ............
Page 10 6.2.1 Timer count register mn (TCRmn) ....................135 6.2.2 Timer data register mn (TDRmn) ....................136 6.3 Registers Controlling Timer Array Unit ..................137 6.3.1 Peripheral enable register 0 (PER0) ....................138 6.3.2 Timer clock select register m (TPSm) .................... 139 6.3.3 Timer mode register mn (TMRmn) ....................
Page 11 6.9.1 Operation as one-shot pulse output function .................. 204 6.9.2 Operation as PWM function ......................211 6.9.3 Operation as multiple PWM output function ................... 218 6.10 Cautions When Using Timer Array Unit ................. 226 6.10.1 Cautions when using timer output ....................226 CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ..........
Page 12 9.3.10 A/D test register (ADTES) ......................266 9.3.11 Registers controlling port function of analog input pins ..............267 9.4 A/D Converter Conversion Operations ..................268 9.5 Input Voltage and Conversion Results ..................270 9.6 A/D Converter Operation Modes ....................271 9.6.1 Software trigger mode (select mode, sequential conversion mode) ..........
Page 13 CHAPTER 11 SERIAL ARRAY UNIT ....................308 11.1 Functions of Serial Array Unit ....................309 11.1.1 3-wire serial I/O (CSI00) ....................... 309 11.1.2 UART (UART0) ..........................310 11.2 Configuration of Serial Array Unit ..................311 11.2.1 Shift register ..........................313 11.2.2 Lower 8/9 bits of the serial data register mn (SDRmn) ..............
Page 14 11.6.2 Slave reception ..........................412 11.6.3 Slave transmission/reception ......................419 11.6.4 Calculating transfer clock frequency ..................... 429 11.6.5 Procedure for processing errors that occurred during slave select input function communication ..........................431 11.7 Operation of UART (UART0) Communication ............... 432 11.7.1 UART transmission ........................
Page 15 12.5.14 Communication reservation ......................501 12.5.15 Cautions ............................. 505 12.5.16 Communication operations ......................506 12.5.17 Timing of I C interrupt request (INTIICAn) occurrence ............... 513 12.6 Timing Charts ........................... 534 CHAPTER 13 DMA CONTROLLER ..................... 549 13.1 Functions of DMA Controller ....................549 13.2 Configuration of DMA Controller ....................
Page 16 15.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L) ....581 15.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0) ..............582 15.3.5 Program status word (PSW) ......................583 15.4 Interrupt Servicing Operations ....................584 15.4.1 Maskable interrupt request acknowledgment ................
Page 17 19.4.3 When used as interrupt and reset mode ..................635 19.5 Cautions for Voltage Detector ....................641 CHAPTER 20 SAFETY FUNCTIONS ....................643 20.1 Overview of Safety Functions ....................643 20.2 Registers Used by Safety Functions ..................644 20.3 Operation of Flash memory CRC operation function (high-speed CRC) ......644 20.3.1 Flash memory CRC control register (CRC0CTL) .................
Page 18 23.8 Processing Time for Each Command When PG-FP6 Is in Use (Reference Value) .... 690 CHAPTER 24 ON-CHIP DEBUG FUNCTION ..................691 24.1 Connecting E1, E2, E2 Lite, E20 On-chip Debugging Emulator to RL78/G1P ....691 24.2 On-chip Debug Security ID ...................... 692 24.3 Securing of User Resources ....................
Page 19 CHAPTER 26 INSTRUCTION SET ....................... 697 26.1 Conventions Used in Operation List ..................698 26.1.1 Operand identifiers and specification methods ................698 26.1.2 Description of operation column ....................699 26.1.3 Description of flag operation column .................... 700 26.1.4 PREFIX instruction ........................700 26.2 Operation List ...........................
Page 20: Chapter 1 Outline
R01UH0895EJ0100 RL78/G1P Rev.1.00 RENESAS MCU Nov 29, 2019 CHAPTER 1 OUTLINE 1.1 Features   Minimum instruction execution time can be changed from high speed (0.03125 s: @ 32 MHz operation with high-  speed on-chip oscillator) to low-speed (1 s: @ 1 MHz operation with high-speed on-chip oscillator) ...
Page 21 RL78/G1P CHAPTER 1 OUTLINE  ROM, RAM capacities Note Flash ROM Data Flash 24-pin 32-pin 16 KB 2 KB 1.5 KB R5F11Z7AANA, R5F11Z7ADNA R5F11ZBAAFP, R5F11ZBADFP Note The flash libraries use the on-chip RAM area from FFE20H to FFEFFH and the parts of the RAM area referred to as self RAM (RAM for use in self-programming), which are listed in the table below, for self-programming or rewriting of the data flash memory.
Page 22: List Of Part Numbers
= -40 to +85°C D: Industrial applications, T = -40 to +85°C ROM capacity: A: 16 KB Pin count: 7: 24-pin B: 32-pin RL78/G1P group Memory type: F: Flash memory Renesas MCU Renesas semiconductor product Pin Count Package Data Flash...
Page 23: Pin Configuration (Top View)
RL78/G1P CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 24-pin products  24-pin plastic HWQFN (4 × 4 mm, 0.5 mm pitch) exposed die pad 18 17 16 15 14 13 P30/INTP2/TxD0/TOOLTxD/SO00 P21/ANI1/AV REFM P31/INTP1/RxD0/TOOLRxD/SI00 P20/ANI0/AV REFP P32/INTP3/SCK00 P22/ANI2/ANO0...
Page 24: 32-Pin Products
RL78/G1P CHAPTER 1 OUTLINE 1.3.2 32-pin products  32-pin plastic LQFP (7 × 7 mm, 0.8 mm pitch) 24 23 22 21 20 19 18 17 P27/ANI7 P30/INTP2/TxD0/TOOLTxD/SO00 P26/ANI6 P31/INTP1/RxD0/TOOLRxD/SI00 P25/ANI5 P32/INTP3/SCK00 P21/ANI1/AV P33/TI02/TO02/SSI00 REFM P20/ANI0/AV REFP P22/ANI2/ANO0 P23/ANI3/ANO1 P61/SDAA0/SDAA1...
Page 25: Pin Identification
RL78/G1P CHAPTER 1 OUTLINE 1.4 Pin Identification ANI0 to ANI7, ANI16: Analog input RxD0: Receive data ANO0, ANO1: Analog output SCK00: Serial clock input/output Analog reference voltage SCLA0, SCLA1: Serial clock input/output REFM minus SDAA0, SDAA1: Serial data input/output Analog reference voltage...
Page 26: Block Diagram
RL78/G1P CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.1 24-pin products TIMER ARRAY UNIT (4ch) P10, P12, P13, PORT 1 TI00/TO00/P13 P15, P16 P20 to P23, TI01/TO01/P16 PORT 2 TI02/TO02/P33 PORT 3 P30 to P33 TI03/TO03/P12 PORT 4 WINDOW PORT 6...
Page 27: 32-Pin Products
RL78/G1P CHAPTER 1 OUTLINE 1.5.2 32-pin products TIMER ARRAY UNIT (4ch) TI00/TO00/P13 PORT 1 P10 to P17 TI01/TO01/P16 PORT 2 P20 to P27 TI02/TO02/P33 PORT 3 P30 to P35 TI03/TO03/P12 PORT 4 WINDOW PORT 6 P60, P61 WATCHDOG TIMER PORT 12...
Page 28: Outline Of Functions
RL78/G1P CHAPTER 1 OUTLINE 1.6 Outline of Functions (1/2) Item 24-pin 32-pin R5F11Z7AANA, R5F11Z7ADNA R5F11ZBAAFP, R5F11ZBADFP Code flash memory 16 KB Data flash memory 2 KB Note 1.5 KB Memory space 1 MB Main system High-speed X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
Page 29 RL78/G1P CHAPTER 1 OUTLINE (2/2) Item 24-pin 32-pin R5F11Z7AANA, R5F11Z7ADNA R5F11ZBAAFP, R5F11ZBADFP  Reset by RESET pin Reset  Internal reset by watchdog timer  Internal reset by power-on-reset  Internal reset by voltage detector  Internal reset by illegal instruction execution Note ...
Page 30: Chapter 2 Pin Functions
RL78/G1P CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List Pin I/O buffer power supplies are unique for all products. The relationship between these power supplies and the pins is shown below. The input and output, buffer, and pull-up resistor settings for each port are also valid for the alternate function.
Page 31: 24-Pin Products
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.1.1 24-pin products Function Name Function After Reset Alternate Function Port 1. Input port ANI16 5-bit I/O port. TI03/TO03/INTP4/P Input/output can be specified in 1-bit units. CLBUZ0 Use of an on-chip pull-up resistor can be specified by a software TI00/TO00 setting at input port.
Page 32: 32-Pin Products
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.1.2 32-pin products Function Name Function After Reset Alternate Function  Port 1. Input port 8-bit I/O port.  Input/output can be specified in 1-bit units. TI03/TO03/INTP4/ Use of an on-chip pull-up resistor can be specified by a software PCLBUZ0 setting at input port.
Page 33: Functions Other Than Port Pins
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.2 Functions Other Than Port Pins 2.2.1 With functions for each product Function Name 32-pin 24-pin Function Name 32-pin 24-pin     ANI0 TO03     ANI1 TxD0   ...
Page 34: Function Descriptions
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.2.2 Function descriptions (1/2) Function Name Function ANI0 Input A/D converter analog input ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI16 ANO0 Output D/A converter output ANO1 Input Negative reference voltage input of the A/D converter...
Page 35 RL78/G1P CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Function  Resonator connection for main system clock  EXCLK Input External clock input for main system clock  Positive power supply for all pins  Ground potential for all pins TOOLRxD...
Page 36: Description Of Pin Functions
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Pin Function List. 2.3.1 P10 to P17 (port 1) P10 to P17 function as an I/O port. These pins also function as timer I/O, external interrupt request input, and clock/buzzer output.
Page 37: P30 To P35 (Port 3)
RL78/G1P CHAPTER 2 PIN FUNCTIONS (a) ANI0 to ANI7 These are the analog input pins (ANI0 to ANI7) of A/D converter. See 9.10 (5) Analog input (ANIn) pins. (b) AV REFP This is a pin that inputs the A/D converter reference potential (+ side).
Page 38: P40 (Port 4)
RL78/G1P CHAPTER 2 PIN FUNCTIONS (h) TI02 This is a pin for inputting an external count clock/capture trigger to 16-bit timer 02. TO02 This is a timer output pin from 16-bit timer 02. TOOLTxD This is the UART serial data output pin for the external device connection used during flash memory programming.
Page 39: P60, P61 (Port 6)
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.3.5 P60, P61 (port 6) P60 and P61 function as an I/O port. These pins also function as serial interface data I/O and clock I/O. Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
Page 40: P137 (Port 13)
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.3.7 P137 (port 13) P137 functions as an input port. P137 pin also functions as external interrupt request input. (1) Port mode P137 functions as an input port. (2) Control mode P137 functions as external interrupt request input.
Page 41: Connection Of Unused Pins
RL78/G1P CHAPTER 2 PIN FUNCTIONS 2.4 Connection of Unused Pins Table 2-3 shows the connection of unused pins. Table 2-3. Connection of Unused Pins Recommended Connection of Unused Pins Pin Name I/O Circuit Type P10/ANI16 Note 1 11-U Input: Independently connect to V or V via a resistor.
Page 42 RL78/G1P CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 8-R pullup P-ch enable data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics output N-ch disable Type 11-G Type 11-T data P-ch IN/OUT data P-ch output...
Page 43 RL78/G1P CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 11-U Type 13-R pull-up P-ch enable data P-ch IN/OUT IN/OUT output N-ch data disable N-ch output disable input enable P-ch Comparator N-ch Series resistor string voltage Type 37-C...
Page 44: Chapter 3 Cpu Architecture
RL78/G1P CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/G1P can access a 1 MB address space. Figure 3-1 shows the memory map. R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 45 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map FFFFF H 0 3 F F F H Special function registers (SFR) 256 bytes FFF00 H FFEFFH General-purpose registers 32 bytes FFEE0H FFEDFH Notes 1, 2, 4 1.5 KB FF9 00 H...
Page 46 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 03FFFH Block 0FH...
Page 47 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Number 00000H to 003FFH 00400H to 007FFH...
Page 48: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/G1P products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM...
Page 49 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table Vector Table Address Interrupt Source 00000H RESET, POR, LVD, WDT, TRAP, IAW, RPE 00004H INTWDTI 00006H INTLVI 00008H INTP0 0000AH INTP1 0000CH INTP2 0000EH INTP3 00010H INTP4 00012H INTP5 00014H INTAD...
Page 50: Mirror Area
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The RL78/G1P mirrors the code flash area of 02000H to 03FFFH, F2000H to F3FFFH. By reading data from F2000H to F3FFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code.
Page 51 RL78/G1P CHAPTER 3 CPU ARCHITECTURE  Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F2000H to F3FFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 52: Internal Data Memory Space
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/G1P products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number Internal RAM 1536  8 bits (FF900H to FFEFFH) RL78/G1P The internal RAM can be used as a data area and a program area where instructions are fetched (it is prohibited to use the general-purpose register area for fetching instructions).
Page 53: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G1P, based on operability and other considerations. In particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use. Figures 3-3 shows correspondence between data memory and addressing.
Page 54: Processor Registers
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/G1P products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 55 Programming Library Type 01 User’s Manual and RL78 Family Data Flash Library Type 04 User’s Manual. RL78/G1P: FFE20H to FFEFFH 4. The flash libraries use the parts of the RAM area referred to as self RAM in self-programming or rewriting of the data flash memory. For the sizes of the RAM areas used by the flash libraries, see “ROM, RAM capacities”...
Page 56: General-Purpose Registers
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Page 57: And Cs Registers
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register indirect addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Page 58: Special Function Registers (Sfrs)
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 59 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register (SFR) List (1/3) Manipulable Bit Range Address Special Function Register (SFR) Name Symbol After Reset 1-bit 8-bit 16-bit    FFF01H Port register 1    FFF02H Port register 2 ...
Page 60 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register (SFR) (2/3) Manipulable Bit Range Address Special Function Register (SFR) Name Symbol After Reset 1-bit 8-bit 16-bit    FFF64H Timer data register 02 TDR02 0000H FFF65H  ...
Page 61 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register (SFR) List (3/3) Manipulable Bit Range Address Special Function Register (SFR) Name Symbol After Reset 1-bit 8-bit 16-bit    FFFE0H Interrupt request flag register 0L IF0L  ...
Page 62: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
Page 63 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended Special Function Register (2nd SFR) List (1/4) Manipulable Bit Range Address Extended Special Function Register Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit    F0010H A/D converter mode register 2 ADM2 ...
Page 64 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended Special Function Register (2nd SFR) List (2/4) Manipulable Bit Range Address Extended Special Function Register Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit    F0110H Serial mode register 00...
Page 65 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended Special Function Register (2nd SFR) List (3/4) Manipulable Bit Range Address Extended Special Function Register Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit    F01A0H Timer status register 00...
Page 66 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended Special Function Register (2nd SFR) List (4/4) Manipulable Bit Range Address Extended Special Function Register Symbol After Reset (2nd SFR) Name 1-bit 8-bit 16-bit    F0300H Event output destination select register 00 ELSELR00 ...
Page 67: Instruction Address Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: 128 to +127 or 32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.
Page 68: Register Indirect Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.
Page 69: Addressing For Processing Data Addresses
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.
Page 70: Direct Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
Page 71: Short Direct Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format]...
Page 72: Sfr Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format]...
Page 73: Register Indirect Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description  [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) ...
Page 74: Based Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
Page 75 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Figure 3-24. Example of [HL+byte], [DE+byte] [HL + byte], [DE + byte] <1> <2> <1> <2> FFFFFH Instruction code Target OP-code Target memory array <2> Offset of data <2> byte <1> Address of Other data in...
Page 76 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Figure 3-27. Example of ES:[HL+byte], ES:[DE+byte] ES: [HL + byte], ES: [DE + byte] <1> <2> <3> <1> <2> <3> XFFFFH Instruction code <2> <3> Target memory Target OP-code array Offset byte of data <3>...
Page 77 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Figure 3-29. Example of ES:word[BC] ES: word [BC] XFFFFH <1> <2> <3> Array of Instruction code Target memory <3> word-sized <3> Offset data OP-code rp(BC) <2> Low Addr. Address of a word within an array <2>...
Page 78: Based Indexed Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address.
Page 79: Stack Addressing
RL78/G1P CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
Page 80 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Figure 3-33. Example of POP POP rp <1> <2> SP+2 <1> SP+1 Stack (SP+1) Instruction code area (SP) <2> OP-code F0000H Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
Page 81 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of RET <1> SP+4 <1> SP+3 (SP+3) Instruction code Stack SP+2 (SP+2) area OP-code SP+1 (SP+1) <3> (SP) <2> F0000H Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
Page 82 RL78/G1P CHAPTER 3 CPU ARCHITECTURE Figure 3-37. Example of RETI, RETB RETI, RETB <1> SP+4 <1> SP+3 (SP+3) Instruction code SP+2 (SP+2) Stack OP-code area SP+1 (SP+1) <3> (SP) <2> F0000H Stack addressing is specified <1>. Memory The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>.
Page 83: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The RL78/G1P microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.
Page 84: Port 1
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 85 RL78/G1P CHAPTER 4 PORT FUNCTIONS For example, figures 4-1 to 4-4 show block diagrams of port 1. Figure 4-1. Block Diagrams of P10 (24-pin products) PU10 P-ch PMC1 PMC10 PORT Output latch P10/ANI16 (P10) PM10 A/D converter Port register 1...
Page 86 RL78/G1P CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P10, P11, P14, and P17 (32-pin products) PU10, PU11, PU14, PU17 P-ch PORT Output latch P10, P11, P14, P17 (P10, P11, P14, P17) PM10, PM11, PM14, PM17 Port register 1...
Page 87 RL78/G1P CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P12, P13, and P16 PU12, PU13, PU16 P-ch Alternate function PORT Output latch P12/TI03/TO03/INTP4/ (P12, P13, P16) PCLBUZ0, P13/TI00/TO00, P16/TI01/TO01/INTP5 PM12, PM13, PM16 Alternate function Port register 1 PU1: Pull-up resistor option register 1...
Page 88 RL78/G1P CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagrams of P15 PU15 P-ch PORT Output latch P15/PCLBUZ1 (P15) PM15 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR: Write signal R01UH0895EJ0100 Rev.1.00...
Page 89: Port 2
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input, (+ side and – side) reference voltage input, and D/A converter output.
Page 90 RL78/G1P CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Functions of P22/ANI2/ANO0, P23/ANI3/ANO1 Pins ADPC Register PM2 Register DAM Register ADS Register P22/ANI2/ANO0, P23/ANI3/ANO1 Pins   Digital I/O selection Input mode Digital input   Output mode Digital output Analog input selection...
Page 91 RL78/G1P CHAPTER 4 PORT FUNCTIONS For example, figures 4-5 and 4-6 show block diagrams of port 2 for 32-pin products. Figure 4-5. Block Diagram of P20, P21, P24 to P27 ADPC ADPC 0: Analog input 1: Digital I/O ADPC0, ADPC1,...
Page 92: Port 3
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P35 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 93 RL78/G1P CHAPTER 4 PORT FUNCTIONS For example, figures 4-7 to 4-11 show block diagrams of port 3 for 32-pin products. Figure 4-7. Block Diagram of P30 PU30 P-ch Alternate function PORT Output latch P30/INTP2/TxD0/ (P30) TOOLTxD/SO00 PM30 Alternate function Port register 3...
Page 94 RL78/G1P CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P31 PU31 P-ch Alternate function PORT Output latch P31/INTP1/RxD0/ (P31) TOOLRxD/SI00 PM31 Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal R01UH0895EJ0100 Rev.1.00...
Page 95 RL78/G1P CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P32 PU32 P-ch Alternate function PORT Output latch P32/INTP3/SCK00 (P32) PM32 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal R01UH0895EJ0100 Rev.1.00...
Page 96 RL78/G1P CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/TI02/TO02/ (P33) SSI00 PM33 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal...
Page 97 RL78/G1P CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P34 and P35 PU34, PU35 P-ch PORT Output latch P34, P35 (P34, P35) PM34, PM35 Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR: Write signal...
Page 98: Port 4
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode using port mode register 4 (PM4). When the P40 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4).
Page 99: Port 6
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The output of the P60 and P61 pins is N-ch open-drain output (6 V tolerance).
Page 100 RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 12 P121 and P122 are 2-bit input only ports. This port can also be used for connecting resonator for main system clock and external clock input for main system clock. Reset signal generation sets port 12 to input mode.
Page 101: Port 13
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 13 P137 is a 1-bit input-only port. P137 is fixed to an input ports. This port can also be used for external interrupt request input. Table 4-10. Settings of Registers When Using Port 13...
Page 102: Registers Controlling Port Function
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers.  Port mode registers (PMxx)  Port registers (Pxx)  Pull-up resistor option registers (PUxx)  Port mode control register 1 (PMC1) ...
Page 103 RL78/G1P CHAPTER 4 PORT FUNCTIONS Table 4-11. PMxx, Pxx, PUxx, PMC1 Registers and Bits Mounted on Each Product (2/2) Bit Name Port PMxx PUxx PMC1 Register Register Register Register    Port 4 PM40 PU40    ...
Page 104: Port Mode Registers (Pmxx)
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
Page 105: Port Registers (Pxx)
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...
Page 106: Pull-Up Resistor Option Registers (Puxx)
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
Page 107: Port Mode Control Register 1 (Pmc1) (24-Pin Products Only)
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.3.4 Port mode control register 1 (PMC1) (24-pin products only) This register sets the digital I/O/analog input in 1-bit units. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH.
Page 108: A/D Port Configuration Register (Adpc)
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.3.5 A/D port configuration register (ADPC) This register switches the ANI0/P20to ANI7/P27 pins to digital I/O of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction.
Page 109: Port Function Operations
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 110: Settings Of Port Related Register When Using Alternate Function
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Related Register When Using Alternate Function To use the alternate function of a port pin, set the port mode register, and output latch as shown in Table 4-12. Caution If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the unused alternate function must be set to its initial state.
Page 111 RL78/G1P CHAPTER 4 PORT FUNCTIONS Table 4-12. Settings of Port Related Register When Using Alternate Function (2/2) Pin Name Alternate Function PM P Name  INTP2 Input TxD0 Output TOOLTxD Output SO00 Output  INTP1 Input  RxD0 Input ...
Page 112 RL78/G1P CHAPTER 4 PORT FUNCTIONS Table 4-14. Setting Functions of P22/ANI2/ANO0 and P23/ANI3/ANO1 Pins ADPC Register PM2 Register P22/ANI2/ANO0, DAM Register ADS Register P23/ANI3/ANO1 Pins   Input mode Digital input Digital I/O selection   Output mode Digital output Selects ANI.
Page 113: Cautions When Using Port Function
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/G1P. <1> The Pn register is read in 8-bit units.
Page 114: Cautions On Specifying The Pin Settings
RL78/G1P CHAPTER 4 PORT FUNCTIONS 4.6.2 Cautions on specifying the pin settings If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the unused alternate function must be set to its initial state so as to prevent conflicting outputs. For details about the alternate output function, see 4.5 Settings of Port Related Register When Using Alternate Function.
Page 115: Chapter 5 Clock Generator
RL78/G1P CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable.
Page 116: Configuration Of Clock Generator
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC)
Page 117 RL78/G1P CHAPTER 5 CLOCK GENERATOR R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 118: Registers Controlling Clock Generator
RL78/G1P CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency High-speed on-chip oscillator clock frequency External main system clock frequency High-speed system clock frequency : Main system clock frequency MAIN CPU/peripheral hardware clock frequency Low-speed on-chip oscillator clock frequency 5.3 Registers Controlling Clock Generator...
Page 119 RL78/G1P CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H Symbol EXCLK OSCSEL AMPH EXCLK OSCSEL High-speed system clock X1/P121 pin X2/EXCLK/P122 pin pin operation mode Input port mode Input port...
Page 120: System Clock Control Register (Ckc)
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 121: Clock Operation Status Control Register (Csc)
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock and high-speed on-chip oscillator clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 122: Oscillation Stabilization Time Counter Status Register (Ostc)
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.3.4 Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case, ...
Page 123 RL78/G1P CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status...
Page 124: Oscillation Stabilization Time Select Register (Osts)
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS register after the STOP mode is released.
Page 125 RL78/G1P CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz = 20 MHz  ...
Page 126: Peripheral Enable Registers 0, 1 (Per0, Per1)
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable registers 0, 1 (PER0, PER1) These registers are used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a hardware that is not in use is stopped in order to reduce power consumption and noise.
Page 127 RL78/G1P CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2) Address: F00F0H After reset: 00H Symbol <6> <5> <4> <2> <0> PER0 IICA1EN ADCEN IICA0EN SAU0EN TAU0EN SAU0EN Control of serial array unit 0 input clock supply Stops input clock supply.
Page 128: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.3.7 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H).
Page 129: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted.
Page 130: System Clock Oscillator
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
Page 131 RL78/G1P CHAPTER 5 CLOCK GENERATOR Figure 5-12 shows examples of incorrect resonator connection. Figure 5-12. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
Page 132 RL78/G1P CHAPTER 5 CLOCK GENERATOR Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (g) Signals are fetched R01UH0895EJ0100 Rev.1.00...
Page 133: High-Speed On-Chip Oscillator
5.4.2 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/G1P. The frequency can be selected from among 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC).
Page 134: Clock Generator Operation
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1).  Main system clock f MAIN  High-speed system clock f...
Page 135 RL78/G1P CHAPTER 5 CLOCK GENERATOR Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On 10 μs or more Lower limit of the operating voltage range Power supply voltage (V <1> Power-on-reset RESET pin Switched by software Reset processing...
Page 136: Controlling Clock
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 6, 4, 3, 2, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H).
Page 137: Example Of Setting X1 Oscillation Clock
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by...
Page 138: Cpu Clock Status Transition Diagram
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.6.3 CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram Power ON High-speed on-chip oscillator: Woken up X1 oscillation/EXCLK input: Stops (input port mode) ≥...
Page 139 RL78/G1P CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/3) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Page 140 RL78/G1P CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/3) (3) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register...
Page 141 RL78/G1P CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/3) (5)  HALT mode (D) set while CPU is operating with high-speed on-chip oscillator clock (B)  HALT mode (E) set while CPU is operating with high-speed system clock (C)
Page 142: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.6.4 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4. Changing CPU Clock CPU Clock...
Page 143: Time Required For Switchover Of Cpu Clock And System Clock
RL78/G1P CHAPTER 5 CLOCK GENERATOR 5.6.5 Time required for switchover of CPU clock and system clock By setting bit 4 (MCM0) of the system clock control register (CKC), the main system clock can be switched (between the high-speed on-chip oscillator clock and the high-speed system clock).
Page 144: Resonator And Oscillator Constants
A list of the resonators for which the operation has most recently been verified and their oscillation constants (for reference) is provided on the page for the corresponding product at the Renesas Web site (http://www.renesas.com). Cautions 1. The constants for these oscillator circuits are reference values based on specific environments set up for evaluation by the manufacturers.
Page 145: Chapter 6 Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The number of units or channels of the timer array unit differs, depending on the product. Units Channels 24, 32-pin Unit 0 Channel 0 √ Channel 1 √ Channel 2 √...
Page 146 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT The timer array unit has four 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.
Page 147: Functions Of Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
Page 148: Simultaneous Channel Operation Function
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (6) Delay counter Counting is started at the valid edge of the signal input to the timer input pin (TImn), and an interrupt is generated after any delay period. Compare operation Timer input Interrupt signal...
Page 149: 8-Bit Timer Operation Function (Channels 1 And 3 Only)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to three types of PWM signals that have a specific period and a specified duty factor can be generated.
Page 150: Configuration Of Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn)
Page 151 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-1. Entire Configuration of Timer Array Unit 0 Timer clock select register 0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Prescaler to f Peripheral enable Selector Selector...
Page 152 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channel 0 of Timer Array Unit 0 Timer CK00 TCLK Output controller controller TO00 Mode CK01 Output latch selection (Pxx) PMxx Interrupt controller INTTM00 (Timer interrupt) Edge Timer counter register 00 (TCR00)
Page 153 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Internal Block Diagram of Channel 2 of Timer Array Unit 0 Interrupt signal from master channel Timer CK00 Output controller controller TCLK TO02 CK01 Mode Output latch selection PMxx (Pxx) Interrupt controller...
Page 154: Timer Count Register Mn (Tcrmn)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Page 155: Timer Data Register Mn (Tdrmn)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
Page 156: Registers Controlling Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers.  Peripheral enable register 0 (PER0)  Timer clock select register m (TPSm)  Timer mode register mn (TMRmn) ...
Page 157: Peripheral Enable Register 0 (Per0)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) The PER0 register is used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a hardware that is not in use is stopped in order to reduce power consumption and noise.
Page 158: Timer Clock Select Register M (Tpsm)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1 , CKm2, CKm3) that are commonly supplied to each channel from external prescaler. CKm1 is selected by using bits 7 to 4 of the TPSm register, and CKm0 is selected by using bits 3 to 0.
Page 159 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register m (TPSm) (1/2) Address: F01B6H, F01B7H (TPS0) After reset: 0000H Symbol TPSm Selection of operation clock (CKmk) (k = 0, 1) Note = 2 MHz = 5 MHz f...
Page 160 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register m (TPSm) (2/2) Address: F01B6H, F01B7H (TPS0) After reset: 0000H Symbol TPSm Selection of operation clock (CKm2) Note = 2 MHz = 5 MHz f = 10 MHz f...
Page 161: Timer Mode Register Mn (Tmrmn)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (f select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
Page 162 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03) After reset: 0000H Symbol MAST TMRmn ERmn (n = 2) Symbol TMRmn SPLIT (n = 1, 3)
Page 163 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03) After reset: 0000H Symbol MAST TMRmn ERmn (n = 2) Symbol TMRmn SPLIT (n = 1, 3)
Page 164 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03) After reset: 0000H Symbol MAST TMRmn ERmn (n = 2) Symbol TMRmn SPLIT (n = 1, 3)
Page 165 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03) After reset: 0000H Symbol MAST TMRmn ERmn (n = 2) Symbol TMRmn SPLIT (n = 1, 3)
Page 166: Timer Status Register Mn (Tsrmn)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B).
Page 167: Timer Channel Enable Status Register M (Tem)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm).
Page 168: Timer Channel Start Register M (Tsm)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1.
Page 169: Timer Channel Stop Register M (Ttm)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0.
Page 170: Timer Input Select Register 0 (Tis0)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 1 of unit 0 timer input. The TIS0 register can be set by an 8-bit memory manipulation instruction.
Page 171: Timer Output Enable Register M (Toem)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
Page 172: Timer Output Register M (Tom)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel.
Page 173: Timer Output Level Register M (Tolm)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1).
Page 174: Timer Output Mode Register M (Tomm)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
Page 175: Noise Filter Enable Register 1 (Nfen1)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
Page 176: Port Mode Registers 1, 3 ( Pm1, Pm3)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Port mode registers 1, 3 ( PM1, PM3) These registers set input/output of ports 1 and 3 in 1-bit units. When using the ports (such as P13/TO00/TI00, and P33/TO02/TI02/SSI00) to be shared with the timer output pin for timer output, set the port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Page 177: Basic Rules Of Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
Page 178 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Example 1 TAU0 Channel group (simultaneous channel CK00 Channel 0: Master operation function) CK01 Channel 1: Independent channel operation function * A channel that operates independent channel operation function may be between Channel 2: Slave a master and a slave of channel group.
Page 179: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8- bit timer channels.
Page 180: Operation Of Counter
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCSmn bit of timer mode register TCLK mn (TMRmn).
Page 181 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TImn pin and...
Page 182: Start Timing Of Counter
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-5.
Page 183: Operation Of Counter
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 184 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
Page 185 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 186 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected.
Page 187 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
Page 188: Channel Output (Tomn Pin) Control
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TOmn pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-30. Output Circuit Configuration <5> TOmn register Interrupt signal of the master channel (INTTMmn) TOmn pin Interrupt signal of the slave channel...
Page 189: Tomn Pin Output Setting
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn pin output setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-31. Status Transition from Timer Output Setting to Operation Start...
Page 190: Cautions On Channel Output Operation
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on channel output operation (1) Changing values set in the registers TOm, TOEm, and TOLm during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn))
Page 191 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
Page 192 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output)) When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m (TOLm) setting.
Page 193 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
Page 194 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-35. Set/Reset Timing Operating Statuses (1) Basic operation timing TCLK INTTMmn Internal reset Master signal channel TOmn pin/ TOmn Toggle Toggle Internal set signal 1 clock delay INTTMmp Slave channel Internal reset signal...
Page 195: Collective Manipulation Of Tomn Bit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
Page 196: Timer Interrupt And Tomn Pin Output At Operation Start
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer interrupt and TOmn pin output at operation start In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start.
Page 197: Timer Input (Timn) Control
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.7 Timer Input (TImn) Control 6.7.1 TImn input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller.
Page 198: Cautions On Channel Input Operation
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.
Page 199: Independent Channel Operation Function Of Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.8 Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
Page 200 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-41. Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 Note Operation clock Timer counter Output CKm0 TOmn pin register mn (TCRmn) controller Interrupt Timer data Interrupt signal TSmn controller register mn(TDRmn) (INTTMmn) Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Page 201 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
Page 202 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode)
Page 203 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 204 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to stop be held is set to the port register.
Page 205: Operation As External Event Counter
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt.
Page 206 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn 0000H TDRmn 0003H 0002H INTTMmn 4 events 4 events 3 events Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 3) 2.
Page 207 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
Page 208 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode).
Page 209 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 210: Operation As Input Pulse Interval Measurement
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit is set to 1.
Page 211 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Remarks 1. m: Unit number (m = 0)n: Channel number (n = 0 to 3) 2.
Page 212 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n...
Page 213 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 214: Operation As Input Signal High-/Low-Level Width Measurement
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input signal high-/low-level width measurement By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the following expression.
Page 215 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CKm1 Operation clock Note Timer counter CKm0 register mn (TCRmn) TNFENmn Timer data Interrupt NFEN1 Noise Edge Interrupt signal TImn pin register mn (TDRmn)
Page 216 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 110B: Capture &...
Page 217 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 218: Operation As Delay Counter
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval.
Page 219 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn INTTMmn Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 3) 2.
Page 220 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n...
Page 221 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode).
Page 222 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 223: Simultaneous Channel Operation Function Of Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.9 Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin.
Page 224 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 TNFENmn TSmn Timer data Interrupt Interrupt signal register mn (TDRmn)
Page 225 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Remarks 1.
Page 226 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
Page 227 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3...
Page 228 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 229 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.
Page 230: Operation As Pwm Function
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
Page 231 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal TSmn register mn (TDRmn) controller (INTTMmn)
Page 232 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Remark 1. m: Unit number (m = 0), n: Master channel number (n = 0, 2) p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3) 2.
Page 233 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
Page 234 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1...
Page 235 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 236 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer...
Page 237: Operation As Multiple Pwm Output Function
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
Page 238 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal...
Page 239 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H...
Page 240 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0), n: Master channel number (n = 0, 2) p: Slave channel number 1, q: Slave channel number 2 n < p < q  3 (Where p and q are integers greater than n) 2.
Page 241 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) MASTER TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3...
Page 242 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (a) Timer mode register mp, mq (TMRmp, TMRmq) TMRmp Note CKSmp1 CKSmp0...
Page 243 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Input clock supply for timer array unit 0 is stopped. default (Clock supply is stopped and writing to each register is setting disabled.)
Page 244 RL78/G1P CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Hardware Status Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when start resuming operation.) The TSmn bit (master), and TSmp and TSmq (slave) bits...
Page 245: Cautions When Using Timer Array Unit
RL78/G1P CHAPTER 6 TIMER ARRAY UNIT 6.10 Cautions When Using Timer Array Unit 6.10.1 Cautions when using timer output Depends on products, a pin is assigned as a timer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status.
Page 246: Chapter 7 Clock Output/Buzzer Output Controller
RL78/G1P CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs.
Page 247 RL78/G1P CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 7-1. Block Diagram of Clock Output/Buzzer Output Controller Internal bus Clock output select register 1 (CKS1) PCLOE1 CCS12 CCS11 CCS10 Prescaler MAIN PCLOE1 to f MAIN MAIN Note PCLBUZ1 /P15 Clock/buzzer controller...
Page 248: Configuration Of Clock Output/Buzzer Output Controller
RL78/G1P CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 7-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select registers n (CKSn)
Page 249 RL78/G1P CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 7-2. Format of Clock Output Select Register n (CKSn) Address: FFFA5H (CKS0), FFFA6H (CKS1) After reset: 00H Symbol <7> CKSn PCLOEn CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZn pin output enable/disable specification Output disable (default)
Page 250: Registers Controlling Port Functions Of Pins To Be Used For Clock Or Buzzer Output
RL78/G1P CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.3.2 Registers controlling port functions of pins to be used for clock or buzzer output Using a port pin for clock or buzzer output requires setting of the registers that control the port functions multiplexed on the target pin (port mode register (PMxx), port register (Pxx)).
Page 251: Operations Of Clock Output/Buzzer Output Controller
RL78/G1P CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 7.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
Page 252: Chapter 8 Watchdog Timer
RL78/G1P CHAPTER 8 WATCHDOG TIMER CHAPTER 8 WATCHDOG TIMER 8.1 Functions of Watchdog Timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.
Page 253: Configuration Of Watchdog Timer
RL78/G1P CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 8-1. Configuration of Watchdog Timer Item Configuration Counter Internal counter (17 bits) Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.
Page 254: Register Controlling Watchdog Timer
RL78/G1P CHAPTER 8 WATCHDOG TIMER 8.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 8.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
Page 255: Operation Of Watchdog Timer
RL78/G1P CHAPTER 8 WATCHDOG TIMER 8.4 Operation of Watchdog Timer 8.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (000C0H).  Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 22).
Page 256: Setting Overflow Time Of Watchdog Timer
RL78/G1P CHAPTER 8 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0...
Page 257: Setting Window Open Period Of Watchdog Timer
RL78/G1P CHAPTER 8 WATCHDOG TIMER 8.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows.
Page 258 RL78/G1P CHAPTER 8 WATCHDOG TIMER The window open period can be set is as follows. Table 8-4. Setting Window Open Period of Watchdog Timer WINDOW1 WINDOW0 Window Open Period of Watchdog Timer Setting prohibited 100% Caution When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100% regardless of the values of the WINDOW1 and WINDOW0 bits.
Page 259: Setting Watchdog Timer Interval Interrupt
RL78/G1P CHAPTER 8 WATCHDOG TIMER 8.4.4 Setting watchdog timer interval interrupt Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75% of the overflow time + 1/2f is reached.
Page 260: Chapter 9 A/D Converter
RL78/G1P CHAPTER 9 A/D CONVERTER CHAPTER 9 A/D CONVERTER The number of analog input channels of the A/D converter differs, depending on the product. 24-pin 32-pin Analog input channels Total 6 ch 8 ch High accuracy channel 5 ch 8 ch...
Page 261 RL78/G1P CHAPTER 9 A/D CONVERTER Various A/D conversion modes can be specified by using the mode combinations below. Trigger Mode Software trigger Conversion is started by software. Hardware trigger no-wait mode Conversion is started by detecting a hardware trigger. Hardware trigger wait mode...
Page 262 RL78/G1P CHAPTER 9 A/D CONVERTER R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 263: Configuration Of A/D Converter
RL78/G1P CHAPTER 9 A/D CONVERTER 9.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 and ANI16 pins These are the analog input pins of the 9 channels of the A/D converter. They input analog signals to be converted into digital signals.
Page 264 RL78/G1P CHAPTER 9 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
Page 265: Registers Controlling A/D Converter
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3 Registers Controlling A/D Converter The A/D converter is controlled by the following registers.  Peripheral enable register 0 (PER0)  A/D converter mode register 0 (ADM0)  A/D converter mode register 1 (ADM1)  A/D converter mode register 2 (ADM2) ...
Page 266: Peripheral Enable Register 0 (Per0)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.1 Peripheral enable register 0 (PER0) The PER0 register is used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a hardware that is not in use is stopped in order to reduce power consumption and noise.
Page 267: A/D Converter Mode Register 0 (Adm0)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 268 RL78/G1P CHAPTER 9 A/D CONVERTER Table 9-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Conversion stopped state Conversion standby state Setting prohibited Conversion-in-progress state Table 9-2. Setting and Clearing Conditions for ADCS Bit A/D Conversion Mode...
Page 269 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Conversion Conversion Conversion Conversion standby operation stopped standby Software ADCS Note 1 trigger mode Cleared by writing 0 to the ADCS bit or automatically upon Set by writing 1 to completion of A/D conversion.
Page 270 RL78/G1P CHAPTER 9 A/D CONVERTER Table 9-3. A/D Conversion Time Selection (1/4) (1) A/D conversion times for 12-bit A/D conversion when there is no power supply stabilization wait time (for software trigger mode and hardware trigger no-wait mode) A/D Converter Mode...
Page 271 RL78/G1P CHAPTER 9 A/D CONVERTER Table 9-3. A/D Conversion Time Selection (2/4) (2) A/D conversion times for 12-bit A/D conversion when there is power supply stabilization wait time (for hardware trigger wait mode (except for the second and subsequent conversions...
Page 272 RL78/G1P CHAPTER 9 A/D CONVERTER Table 9-3. A/D Conversion Time Selection (3/4) (3) A/D conversion times for 8-bit A/D conversion when there is no power supply stabilization wait time (for software trigger mode and hardware trigger no-wait mode) A/D Converter Mode...
Page 273 RL78/G1P CHAPTER 9 A/D CONVERTER Table 9-3. A/D Conversion Time Selection (4/4) (4) A/D conversion times for 8-bit A/D conversion when there is power supply stabilization wait time (for hardware trigger wait mode (except for the second and subsequent conversions...
Page 274 RL78/G1P CHAPTER 9 A/D CONVERTER Cautions 4. In hardware trigger wait mode, make settings that affect the conversion time such that the following conditions are satisfied.  f must be in the range from 1 to 16 MHz.  When the setting of the ADISS bit of the ADS register is 1, selecting the temperature sensor or internal reference voltage output, the following condition applies.
Page 275 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ADCS  1 or ADS rewrite ADCS Sampling timing INTAD Sampling Sampling Successive conversion Transfer to ADCR, clear clear INTAD generation...
Page 276: A/D Converter Mode Register 1 (Adm1)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 277: A/D Converter Mode Register 2 (Adm2)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.4 A/D converter mode register 2 (ADM2) This register is used to select the + side or - side reference voltage of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode.
Page 278 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H Symbol <3> <2> <0> ADM2 ADREFP1 ADREFP0 ADREFM ADRCK ADTYP Selection of the  side reference voltage source of the A/D converter...
Page 279 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-8. ADRCK Bit Interrupt Signal Generation Range ADCR register value (A/D conversion result) 1111111111B AREA 3 INTAD is generated (ADUL < ADCR) when ADRCK = 1. ADUL register setting INTAD is generated AREA 1 when ADRCK = 0.
Page 280: 12-Bit A/D Conversion Result Register (Adcr)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.5 12-bit A/D conversion result register (ADCR) The higher 4 bits are fixed to 0. Each time A/D conversion ends, each time A/D conversion ends, the value of ADSAR [11:0] is stored in the A/D conversion result register (note that whether to store this value is determined by the setting of the ADRCK bit of the ADM2 register and by the settings of the ADUL and ADLL registers).
Page 281: 8-Bit A/D Conversion Result Register (Adcrh)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that indicate [11:4] bits of ADCR register. The higher 8 bits of 12-bit resolution are stored Note The ADCRH register can be read by an 8-bit memory manipulation instruction.
Page 282: Analog Input Channel Specification Register (Ads)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 283 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-11. Format of Analog Input Channel Specification Register (ADS) (2/2) Address: FFF31H After reset: 00H Symbol ADISS ADS4 ADS2 ADS1 ADS0  Scan mode (ADMD = 1) ADISS ADS4 ADS2 ADS1 ADS0 Analog input channel...
Page 284: Conversion Result Comparison Upper Limit Setting Register (Adul)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 9-8).
Page 285: A/D Test Register (Adtes)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage or  side reference voltage of the A/D converter, or the analog input channel (ANIxx), the temperature sensor output voltage, or the internal reference voltage (1.45 V) as the A/D conversion target for the A/D test function.
Page 286: Registers Controlling Port Function Of Analog Input Pins
RL78/G1P CHAPTER 9 A/D CONVERTER 9.3.11 Registers controlling port function of analog input pins Set up the registers for controlling the functions of the ports shared with the analog input pins of the A/D converter (port mode registers (PMxx), port mode control registers 1 (PMC1), and A/D port configuration register (ADPC)). For details, see 4.3.1 Port mode registers (PMxx), 4.3.4 Port mode control register 1 (PMC1) (24-pin products only), and 4.3.5...
Page 287: A/D Converter Conversion Operations
RL78/G1P CHAPTER 9 A/D CONVERTER 9.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
Page 288 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-15. Conversion Operation of A/D Converter (Software Trigger Mode) ADCS  1 or ADS rewrite Conversion time Sampling time A/D converter SAR clear A/D conversion Sampling operation Conversion result Undefined Conversion ADCR result INTAD In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
Page 289: Input Voltage And Conversion Results
RL78/G1P CHAPTER 9 A/D CONVERTER 9.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7, ANI16) and the theoretical A/D conversion result (stored in the 12-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 290: A/D Converter Operation Modes
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 9.7 A/D Converter Setup Flowchart. 9.6.1 Software trigger mode (select mode, sequential conversion mode) <1>...
Page 291: Software Trigger Mode (Select Mode, One-Shot Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 292: Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 293: Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 294: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 295: Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 296: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 297: Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 298: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 299: Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 300: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 301: Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
RL78/G1P CHAPTER 9 A/D CONVERTER 9.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 302: A/D Converter Setup Flowchart
RL78/G1P CHAPTER 9 A/D CONVERTER 9.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 303: Setting Up Software Trigger Mode
RL78/G1P CHAPTER 9 A/D CONVERTER 9.7.1 Setting up software trigger mode Figure 9-29. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input.
Page 304: Setting Up Hardware Trigger No-Wait Mode
RL78/G1P CHAPTER 9 A/D CONVERTER 9.7.2 Setting up hardware trigger no-wait mode Figure 9-30. Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 305: Setting Up Hardware Trigger Wait Mode
RL78/G1P CHAPTER 9 A/D CONVERTER 9.7.3 Setting up hardware trigger wait mode Figure 9-31. Setting up Hardware Trigger Wait Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.
Page 306: Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected
RL78/G1P CHAPTER 9 A/D CONVERTER 9.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected (example for software trigger mode and one-shot conversion mode) Figure 9-32. Setup when temperature sensor output voltage/internal reference voltage is selected Start of setup...
Page 307: Setting Up Test Mode
RL78/G1P CHAPTER 9 A/D CONVERTER 9.7.5 Setting up test mode Figure 9-33. Setting up Test Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.  ADM0 register FR2 to FR0, and LV0 bits: These are used to specify the A/D conversion time.
Page 308: Snooze Mode Function
RL78/G1P CHAPTER 9 A/D CONVERTER 9.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger.
Page 309 RL78/G1P CHAPTER 9 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
Page 310 RL78/G1P CHAPTER 9 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.
Page 311 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-37. Flowchart for Setting up SNOOZE Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.
Page 312: How To Read A/D Converter Characteristics Table
RL78/G1P CHAPTER 9 A/D CONVERTER 9.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 313 RL78/G1P CHAPTER 9 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale  3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 314: Cautions For A/D Converter
RL78/G1P CHAPTER 9 A/D CONVERTER 9.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
Page 315 RL78/G1P CHAPTER 9 A/D CONVERTER Figure 9-44. Analog Input Pin Connection If there is a possibility that noise equal to or higher than and V , or equal to or lower than AV and V REFP REFM may enter, clamp with a diode with a small V value (0.3 V or lower).
Page 316 RL78/G1P CHAPTER 9 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may be set just before the ADS register rewrite.
Page 317 RL78/G1P CHAPTER 9 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 9-46. Internal Equivalent Circuit of ANIn Pin ANIn Table 9-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) ANIn Pin R1[k]...
Page 318: Chapter 10 D/A Converter
RL78/G1P CHAPTER 10 D/A CONVERTER CHAPTER 10 D/A CONVERTER The D/A converter is a 10-bit resolution R-2R type unit that converts digital inputs into analog signals. It is used to control analog outputs for two independent channels. 10.1 Function of D/A Converter The D/A converter has the following features.
Page 319: Configuration Of D/A Converter
RL78/G1P CHAPTER 10 D/A CONVERTER 10.2 Configuration of D/A Converter The D/A converter includes the following hardware. Table 10-1. Configuration of D/A Converter Item Configuration Control registers A/D port configuration register (ADPC) Peripheral enable register 1 (PER1) D/A converter mode register (DAM)
Page 320: Configuration Of A/D Converter
RL78/G1P CHAPTER 10 D/A CONVERTER 10.3 Configuration of A/D Converter The D/A converter uses the following registers.  A/D port configuration register (ADPC)  Peripheral enable register 1 (PER1)  D/A converter mode register (DAM)  D/A conversion value setting registers 0, 1 (DACS0, DACS1) ...
Page 321: Peripheral Enable Register 1 (Per1)
RL78/G1P CHAPTER 10 D/A CONVERTER 10.3.2 Peripheral enable register 1 (PER1) The PER1 register is used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a hardware that is not in use is stopped in order to reduce power consumption and noise.
Page 322: D/A Converter Mode Register (Dam)
RL78/G1P CHAPTER 10 D/A CONVERTER 10.3.3 D/A converter mode register (DAM) This register controls the operation of the D/A converter. The DAM register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 323: Port Mode Register 2 (Pm2)
RL78/G1P CHAPTER 10 D/A CONVERTER 10.3.5 Port mode register 2 (PM2) When using ANO0/ANI2/P22 and ANO1/ANI3/P23 pins as analog input ports, set bits PM22 and PM23 to 1. If bits PM22 and PM23 are set to 0, these pins cannot be used as analog input ports.
Page 324: Operations Of D/A Converter
RL78/G1P CHAPTER 10 D/A CONVERTER 10.4 Operations of D/A Converter 10.4.1 Operation in normal mode D/A conversion is performed using write operation to the DACSi register as the trigger. The setting method is described below. <1> Set the DACEN bit of the PER1 register (peripheral enable register 1) to 1 to start the supply of the input clock to the D/A converter.
Page 325: Operation In Real-Time Output Mode
RL78/G1P CHAPTER 10 D/A CONVERTER 10.4.2 Operation in real-time output mode D/A conversion is performed on each channel using the individual interrupt request signals from the ELC as triggers. The setting method is described below. <1> Set the DACEN bit of the PER1 register (peripheral enable register 1) to 1 to start the supply of the input clock to the D/A converter.
Page 326: Cautions For D/A Converter
RL78/G1P CHAPTER 10 D/A CONVERTER 10.5 Cautions for D/A Converter Observe the following cautions when using the D/A converter. (1) The digital port I/O function, which is the alternate function of the ANO0 and ANO1 pins, does not operate if the ports are set to analog pins by using the ADPC register (port configuration register).
Page 327: Chapter 11 Serial Array Unit
CHAPTER 11 SERIAL ARRAY UNIT CHAPTER 11 SERIAL ARRAY UNIT Serial array unit 0 has a serial channel that can achieve 3-wire serial (CSI) and UART communication. Function assignment of each channel supported by the RL78/G1P is as shown below. Unit Channel...
Page 328: Functions Of Serial Array Unit
CHAPTER 11 SERIAL ARRAY UNIT 11.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G1P has the following features. 11.1.1 3-wire serial I/O (CSI00) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
Page 329: Uart (Uart0)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.1.2 UART (UART0) This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 330: Configuration Of Serial Array Unit
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 11-1. Configuration of Serial Array Unit Item Configuration Shift register 9 bits Note Buffer register Lower 9 bits of serial data register mn (SDRmn)
Page 331 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-1 shows the block diagram of the serial array unit 0. Figure 11-1. Block Diagram of Serial Array Unit 0 Serial output register 0 (SO0) Noise filter enable register 0 (NFEN0) CKO00 SO00...
Page 332: Shift Register
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.2.1 Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used.
Page 333 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-2. Format of Serial Data Register mn (SDRmn) (mn = 00) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) FFF11H (SDR00) FFF10H (SDR00) SDRmn Shift register Remark For the function of the higher 7 bits of the SDRmn register, see 11.3 Registers Controlling Serial Array Unit.
Page 334: Registers Controlling Serial Array Unit
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers.  Peripheral enable register 0 (PER0)  Serial clock select register m (SPSm)  Serial mode register mn (SMRmn) ...
Page 335: Peripheral Enable Register 0 (Per0)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.1 Peripheral enable register 0 (PER0) The PER0 register is used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a hardware that is not in use is stopped in order to reduce power consumption and noise.
Page 336: Serial Clock Select Register M (Spsm)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0.
Page 337: Serial Mode Register Mn (Smrmn)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock ), specify whether the serial clock (f ) may be input or not, set a start trigger, an operation mode (CSI or UART), and an interrupt source.
Page 338: Serial Communication Operation Setting Register Mn (Scrmn)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-5. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00), F0112H, F0113H (SMR01) After reset: 0020H Symbol SMRmn Note Note Controls inversion of level of receive data of channel n in UART mode Falling edge is detected as the start bit.
Page 339 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00), F011AH, F011BH (SCR01) After reset: 0087H Symbol SCRmn SLCm DLSm Note 1 Setting of operation mode of channel n Disable communication.
Page 340 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00), F011AH, F011BH (SCR01) After reset: 0087H Symbol SCRmn SLCm DLSm Note 1 Setting of parity bit in UART mode...
Page 341: Higher 7 Bits Of The Serial Data Register Mn (Sdrmn)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.5 Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00, SDR01 function as a transmit/receive buffer register, and bits 15 to 9 are used as a...
Page 342: Serial Flag Clear Trigger Register Mn (Sirmn)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.
Page 343: Serial Status Register Mn (Ssrmn)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error.
Page 344 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-9. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01) After reset: 0000H Symbol SSRmn FEFm Note FEFm Framing error detection flag of channel n Note No error occurs.
Page 345: Serial Channel Start Register M (Ssm)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).
Page 346: Serial Channel Stop Register M (Stm)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).
Page 347: Serial Channel Enable Status Register M (Sem)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Page 348: Serial Output Enable Register M (Soem)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
Page 349: Serial Output Register M (Som)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
Page 350: Serial Output Level Register M (Solm)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.13 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode.
Page 351: Serial Standby Control Register M (Sscm)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.14 Serial standby control register m (SSCm) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSCm register can be set by a 16-bit memory manipulation instruction.
Page 352: Input Switch Control Register (Isc)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.15 Input switch control register (ISC) The SSIE00 bit of the ISC register is used to control the SSI00 pin input when CSI00 communication and slave mode are applied. While a high level is being input to the SSI00 pin, no transmission/reception operation is performed even if a serial clock is input, and the SO00 pin outputs high impedance.
Page 353: Noise Filter Enable Register 0 (Nfen0)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.16 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.
Page 354: Port Mode Register 3 (Pm3)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.3.17 Port mode register 3 (PM3) This register sets input/output of port 3 in 1-bit units. When using the ports (such as P30/INTP2/TxD0/TOOLTxD/SO0) to be shared with the serial data output pin or serial clock output pin for serial data output or serial clock output, set the port mode register (PMxx) bit corresponding to each port to 0.
Page 355: Operation Stop Mode
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode.
Page 356: Stopping The Operation By Units
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0). The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 357: Stopping The Operation By Channels
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 11-23. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable stopping communication/count by each channel.
Page 358: Operation Of 3-Wire Serial I/O (Csi00) Communication
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5 Operation of 3-Wire Serial I/O (CSI00) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception]  Data length of 7 or 8 bits ...
Page 359 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00) are channel 0 of SAU0. Unit Channel Used as CSI Used as UART CSI00 (supporting slave UART0 select input function)  3-wire serial I/O (CSI00) performs the following seven types of communication operations.
Page 360: Master Transmission
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.1 Master transmission Master transmission is that the RL78/G1P outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SO00 Interrupt...
Page 361 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 Operation clock (f...
Page 362 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-25. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 363 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-26. Procedure for Stopping Master Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 364 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-27. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation (Essential) Master ready? completed Disable data output and clock output of Port manipulation...
Page 365 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-28. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
Page 366 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-29. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, see Figure 11-25. SAU default setting (Select Transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
Page 367 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-30. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <6> STmn SEmn SDRmn Transmit data 2...
Page 368 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-31. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting <1> For the initial setting, refer to Figure 11-25. SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...
Page 369: Master Reception
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.2 Master reception Master reception is that the RL78/G1P outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SI00 Interrupt...
Page 370 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 Operation clock (f...
Page 371 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-33. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 372 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-34. Procedure for Stopping Master Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 373 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-35. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing master (Essential) completed preparations? Disable clock output of the target channel by setting a port register and a...
Page 374 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11-36. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
Page 375 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-37. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, see Figure 11-33. SAU default setting (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data...
Page 376 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 11-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 377 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-39. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication For the initial setting, refer to Figure 11-33. SAU default setting (Select buffer empty interrupt) <1> Setting storage area of the receive data, number of...
Page 378: Master Transmission/Reception
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.3 Master transmission/reception Master transmission/reception is that the RL78/G1P outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SI00, SO00...
Page 379 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 Operation clock (f...
Page 380 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-41. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 381 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-42. Procedure for Stopping Master Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 382 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-43. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave completed (Essential) preparations? Disable data output and clock output of the target channel by setting a port...
Page 383 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11-44. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
Page 384 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-45. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 11-41. (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data Setting...
Page 385 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11-46. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 386 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 11-41. SAU default setting (Select buffer empty interrupt) <1> Setting storage data and number of data for transmission/reception...
Page 387: Slave Transmission
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.4 Slave transmission Slave transmission is that the RL78/G1P transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0...
Page 388 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 Operation clock (f...
Page 389 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-49. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 390 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-50. Procedure for Stopping Slave Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 391 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-51. Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) (master) preparations? Disable data output of the target channel by setting a port register and a port...
Page 392 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-52. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
Page 393 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-53. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, refer to Figure 11-49. SAU default setting (Select transfer end interrupt) Set storage area and the number of data for transmit data...
Page 394 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-54. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <6> STmn SEmn SDRmn Transmit data 2...
Page 395 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-55. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 11-49. SAU default setting (Select buffer empty interrupt) <1> Set storage area and the number of data for transmit data...
Page 396: Slave Reception
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.5 Slave reception Slave reception is that the RL78/G1P receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0...
Page 397 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 Operation clock (f...
Page 398 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-57. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 399 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-59. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) Completing master (Essential) preparations? Disable clock output of the target channel by setting a port register and a...
Page 400 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11-60. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1...
Page 401 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-61. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, see Figure 11-57. SAU default setting (Select transfer end interrupt only) Clear storage area setting and the number of receive data...
Page 402: Slave Transmission/Reception
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.6 Slave transmission/reception Slave transmission/reception is that the RL78/G1P transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0...
Page 403 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 Operation clock (f...
Page 404 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-63. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 405 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-64. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 406 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-65. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target Completing master (Essential) (master) preparations? Disable data output of the target channel by setting a port register and a port...
Page 407 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11-66. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
Page 408 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-67. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 11-63. SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data...
Page 409 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11-68. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 410 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 11-63. <1> SAU default setting (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception...
Page 411: Snooze Mode Function (Csi00)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.7 SNOOZE mode function (CSI00) SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU operation by detecting SCKp pin input.
Page 412 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-71. Flowchart of SNOOZE Mode Operation (Once Startup) SNOOZE mode operation TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) <1> Write STm0 bit to 1 SMRm0, SCRm0 : Communication setting...
Page 413 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 11-72. Timing Chart of SNOOZE Mode Operation (Continuous Startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation status Normal operation STOP mode SNOOZE mode Normal operation...
Page 414 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-73. Flowchart of SNOOZE Mode Operation (Continuous Startup) SNOOZE operation TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) Write STm0 bit to 1 <1> SMRm0, SCRm0 : Communication setting...
Page 415: Calculating Transfer Clock Frequency
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]...
Page 416 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Table 11-2. Selection of Operation Clock for 3-Wire Serial I/O Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz...
Page 417: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O (Csi00)
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication is described in Figure 11-74. Figure 11-74. Processing Procedure in Case of Overrun Error...
Page 418: Clock Synchronous Serial Communication With Slave Select Input Function
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.6 Clock Synchronous Serial Communication with Slave Select Input Function Channel 0 of SAU0 correspond to the clock synchronous serial communication with slave select input function. [Data transmission/reception]  Data length of 7 or 8 bits ...
Page 419 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Multiple slaves can be connected to a master and communication can be performed by using the slave select input function. The master outputs a slave select signal to the slave (one) that is the other party of communication, and each slave judges whether it has been selected as the other party of communication and controls the SO pin output.
Page 420 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-76. Slave Select Input Function Timing Diagram DAPmn = 0 Transmit data is set BFFmn TSFmn SSEmn SCKmn (CKPmn = 0) SImn bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Sampling timing SOmn...
Page 421: Slave Transmission
RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.6.1 Slave transmission Slave transmission is that the RL78/G1P transmits data to another device in the state of a transfer clock being input from another device. Slave Select Input CSI00 Function Target channel Channel 0 of SAU0...
Page 422 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-77. Example of Contents of Registers for Slave Transmission of Slave Select Input Function (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 423 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-77. Example of Contents of Registers for Slave Transmission of Slave Select Input Function (CSI00) (2/2) (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
Page 424 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-78. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 425 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-79. Procedure for Stopping Slave Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait.)
Page 426 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-80. Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target (master) Completing master or operation completed. (Essential) preparations? Disable data output of the target channel by setting...
Page 427 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-81. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
Page 428 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-82. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, refer to Figure 11-78. SAU default setting (Select transfer end interrupt) Set storage area and the number of data for transmit data...
Page 429 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-83. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <6> STmn SEmn SDRmn Transmit data 2...
Page 430 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-84. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 11-78. SAU default setting (Select buffer empty interrupt) <1> Set storage area and the number of data for transmit data...
Page 431 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.6.2 Slave reception Slave reception is that the RL78/G1P receives data from another device in the state of a transfer clock being input from another device. Slave Select Input CSI00 Function Target channel Channel 0 of SAU0...
Page 432 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-85. Example of Contents of Registers for Slave Reception of Slave Select Input Function (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 433 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-85. Example of Contents of Registers for Slave Reception of Slave Select Input Function (CSI00) (2/2) (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
Page 434 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-86. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 435 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-88. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) Completing master or operation completed. (Essential) preparations? Disable clock output of the target channel by (Essential) Port manipulation setting a port register and a port mode register.
Page 436 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11-89. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1...
Page 437 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-90. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, see Figure 11-86. SAU default setting (Select transfer end interrupt only) Clear storage area setting and the number of receive data...
Page 438 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.6.3 Slave transmission/reception Slave transmission/reception is that the RL78/G1P transmits/receives data to/from another device in the state of a transfer clock being input from another device. Slave Select Input CSI00 Function Target channel Channel 0 of SAU0...
Page 439 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-91. Example of Contents of Registers for Slave Transmission/Reception of Slave Select Input Function (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 440 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-91. Example of Contents of Registers for Slave Transmission/Reception of Slave Select Input Function (CSI00) (2/2) (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
Page 441 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-92. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 442 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-93. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait.) Write 1 to the STmn bit of the target channel.
Page 443 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-94. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target (master) or operation completed. Completing master (Essential) preparations? Disable data output of the target channel by setting...
Page 444 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11-95. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
Page 445 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-96. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 11-92. SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data...
Page 446 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11-97. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 447 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-98. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, see Figure 11-92. <1> SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission...
Page 448 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.6.4 Calculating transfer clock frequency The transfer clock frequency for slave select input function (CSI00) communication can be calculated by the following expressions. (1) Slave Note (Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}...
Page 449 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Table 11-3. Selection of Operation Clock for Slave Select Input Function Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz...
Page 450 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.6.5 Procedure for processing errors that occurred during slave select input function communication The procedure for processing errors that occurred during slave select input function communication is described in Figure 11-99. Figure 11-99. Processing Procedure in Case of Overrun Error...
Page 451 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.7 Operation of UART (UART0) Communication This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 452 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0. Unit Channel Used as CSI Used as UART CSI00 (supporting slave UART0 select input function)  If UART0 is selected for channels 0 and 1 of unit 0, for example, these channels cannot be used for CSI00.
Page 453 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.7.1 UART transmission UART transmission is an operation to transmit data from the RL78/G1P to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
Page 454 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-100. Example of Contents of Registers for UART Transmission of UART (UART0) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn MDmn1 MDmn0 Operation clock (f ) of channel n...
Page 455 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-100. Example of Contents of Registers for UART Transmission of UART (UART0) (2/2) (e) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm0 SOm0  Note 0: Serial data output value is “0”...
Page 456 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-101. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 457 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-102. Procedure for Stopping UART Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 458 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-103. Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target or Completing master communication operation completed (Essential) preparations? Disable data output of the target channel by setting...
Page 459 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-104. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1...
Page 460 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-105. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, refer to Figure 11-101. SAU default setting (Select transfer end interrupt) Set data for transmission and the number of data. Clear...
Page 461 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-106. Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SSmn <6> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin...
Page 462 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-107. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication For the initial setting, refer to Figure 11-101. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...
Page 463 CHAPTER 11 SERIAL ARRAY UNIT 11.7.2 UART reception UART reception is an operation wherein the RL78/G1P asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
Page 464 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-108. Example of Contents of Registers for UART Reception of UART (UART0) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn1 MDmn0 Operation clock (f ) of channel n...
Page 465 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-108. Example of Contents of Registers for UART Reception of UART (UART0) (2/2) (e) Serial output register m (SOm) … The register that not used in this mode. CKOm0 SOm0   (f) Serial output enable register m (SOEm) …The register that not used in this mode.
Page 466 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-109. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
Page 467 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-111. Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait until Completing communication completes its communication operation. (Essential) target preparations? Re-set the register to change the operation clock...
Page 468 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow Figure 11-112. Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 RxDq pin Receive data 1 Receive data 2 Receive data 3...
Page 469 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-113. Flowchart of UART Reception Starting UART communication For the initial setting, refer to Figure 11-109. SAU default setting (setting to mask for error interrupt) Setting storage area of the receive data , number of communication data...
Page 470 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.7.3 SNOOZE mode function SNOOZE mode makes UART operate reception by RxDq pin input detection while the STOP mode. Normally UART stops communication in the STOP mode. But, using the SNOOZE mode makes reception UART operate unless the CPU operation by detecting RxDq pin input.
Page 471 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Table 11-4. Baud Rate Setting for UART Reception in SNOOZE Mode High-speed On-chip Baud Rate for UART Reception in SNOOZE Mode Oscillator (f Baud Rate of 4800 bps Operating clock SDRmn[15:9] Maximum Minimum Permissible Value...
Page 472 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (1) SNOOZE mode operation (Normal operation) Figure 11-114. Timing Chart of SNOOZE Mode Operation (Normal Operation Mode) CPU operation status Normal operation STOP mode Normal operation SNOOZE mode <4> <3> <12> SS01 <1> <10>...
Page 473 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) SNOOZE mode operation (Abnormal Operation <1>) Abnormal operation <1> is the operation performed when a communication error occurs while SSECm = 0. Because SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs.
Page 474 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-116. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>) Setting start Does TSFmn = 0 on all channels? Writing 1 to the STmn bit The operation of all channels is also stopped to switch to the <1>...
Page 475 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) SNOOZE mode operation (Abnormal Operation <2>) Abnormal operation <2> is the operation performed when a communication error occurs while SSECm = 1. Because SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error occurs.
Page 476 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Figure 11-118. Flowchart of SNOOZE Mode Operation (Abnormal Operation <2>) Setting start Does TSFmn = 0 on all channels? SIRm1 = 0007H Clear the all error flags The operation of all channels is also stopped to switch to the Writing 1 to the STmn bit <1>...
Page 477 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Caution When using the SNOOZE mode while SSECm is set to 1, no overrun errors occur. Therefore, when using the SNOOZE mode, read bits 7 to 0 (RxDq) of the SDRm1 register before switching to the STOP mode.
Page 478 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.7.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
Page 479 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT Table 11-5. Selection of Operation Clock for UART Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz...
Page 480 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 481 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 482 RL78/G1P CHAPTER 11 SERIAL ARRAY UNIT 11.7.5 Procedure for processing errors that occurred during UART (UART0) communication The procedure for processing errors that occurred during UART (UART0) communication is described in Figures 11- 120 and 11-121. Figure 11-120. Processing Procedure in Case of Parity Error or Overrun Error...
Page 483 CHAPTER 12 SERIAL INTERFACE IICA CHAPTER 12 SERIAL INTERFACE IICA The RL78/G1P has two units of serial interface IICA and support two slave addresses. When using IICA0 and IICA1 as slaves, the corresponding slave can communicate with the master when either one of the slave addresses matches an address received from the I C bus.
Page 484 Output control Serial clock counter Serial clock Channel 1 controller Caution The RL78/G1P can wait simultaneously because they have channels 0 and 1. However, they cannot communicate simultaneously as they share the P60/SCLA0/SCLA1 and P61/SDAA0/SDAA1 pins. R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 485 Slave CPU3 Master CPU2 Address 3 Slave CPU2 Address 5 Slave IC Address 4 Slave IC Address N Remark The RL78/G1P can communicate supporting two addresses as they have two units of serial interface IICA. R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 486 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 12-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register n (IICAn) Slave address register n (SVAn) Control registers...
Page 487 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (2) Slave address register n (SVAn) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVAn register can be set by an 8-bit memory manipulation instruction.
Page 488 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (11) Start condition generator This circuit generates a start condition when the STTn bit is set to 1. However, in the communication reservation disabled status (IICRSVn bit = 1), when the bus is not released (IICBSYn bit = 1), start condition requests are ignored and the STCFn bit is set to 1.
Page 489 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following eight registers. • Peripheral enable register 0 (PER0) • IICA control register n0 (IICCTLn0) • IICA flag register n (IICFn) •...
Page 490 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.3.2 IICA control register n0 (IICCTLn0) This register is used to enable/stop I C operations, set wait timing, and set other I C operations. The IICCTLn0 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIEn, WTIMn, and ACKEn bits while IICEn = 0 or during the wait period.
Page 491 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register n0 (IICCTLn0) (1/4) Address: F0230H (IICCTL00), F0238H (IICCTL10) After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTLn0 IICEn LRELn WRELn SPIEn WTIMn ACKEn...
Page 492 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register n0 (IICCTLn0) (2/4) Note 1 SPIEn Enable/disable generation of interrupt request when stop condition is detected Disable Enable If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn = 1.
Page 493 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register n0 (IICCTLn0) (3/4) Note STTn Start condition trigger Do not generate a start condition. When bus is released (in standby state, when IICBSYn = 0): If this bit is set (1), a start condition is generated (startup as the master).
Page 494 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register n0 (IICCTLn0) (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing  For master reception: Cannot be set to 1 during transfer.
Page 495 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.3.3 IICA status register n (IICSn) This register indicates the status of I The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the wait period.
Page 496 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-7. Format of IICA Status Register n (IICSn) (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) ...
Page 497 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-7. Format of IICA Status Register n (IICSn) (3/3) ACKDn Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1) ...
Page 498 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-8. Format of IICA Flag Register n (IICFn) Note Address: FFF52H (IICF0), FFF56H (IICF1) After reset: 00H <7> <6> <1> <0> Symbol IICFn STCFn IICBSYn STCENn IICRSVn STCFn STTn clear flag Generate start condition...
Page 499 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.3.5 IICA control register n1 (IICCTLn1) This register is used to set the operation mode of I C and detect the statuses of the SCLAn and SDAAn pins. The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn bits are read-only.
Page 500 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-9. Format of IICA Control Register n1 (IICCTLn1) (2/2) CLDn Detection of SCLAn pin level (valid only when IICEn = 1) The SCLAn pin was detected at low level. The SCLAn pin was detected at high level.
Page 501 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.3.6 IICA low-level width setting register n (IICWLn) This register is used to set the low-level width (t ) of the SCLAn pin signal that is output by serial interface IICA. The data hold time is decided by value the higher 6 bits of IICWL register.
Page 502 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.3.8 Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCLA0/SCLA1 pin as clock I/O and the P61/SDAA0/SDAA1 pin as serial data I/O, clear PM60 and PM61 to 0, and set the output latches of P60 and P61 to 1.
Page 503 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.4 I C Bus Mode Functions 12.4.1 Pin configuration The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows. (1) SCLAn ..This pin is used for serial clock input and output.
Page 504 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.4.2 Setting transfer clock by using IICWLn and IICWHn registers (1) Setting transfer clock on master side Transfer clock = IICWL0 + IICWH0 + f At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
Page 505 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Caution Note the minimum f operation frequency when setting the transfer clock. The minimum f operation frequency for serial interface IICA is determined according to the mode. Fast mode: = 3.5 MHz (MIN.) Fast mode plus: f = 10 MHz (MIN.)
Page 506 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 12-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I bus’s serial data bus.
Page 507 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 508 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
Page 509 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.5 Stop condition When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.
Page 510 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLAn pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
Page 511 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-20. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKEn = 1) Master Master and slave both wait after output of ninth clock...
Page 512 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.7 Canceling wait The I C usually cancels a wait state by the following processing.  Writing data to the IICA shift register n (IICAn)  Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) ...
Page 513 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.8 Interrupt request (INTIICAn) generation timing and wait control The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is generated and the corresponding wait control, as shown in Table 12-2.
Page 514 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.9 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICAn) occurs when the address set to the slave address register n (SVAn) matches the slave address sent by the master device, or when an extension code has been received.
Page 515 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STTn bit is set to 1 before the STDn bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 516 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Table 12-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission...
Page 517 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIICAn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICAn signal from occurring when addresses do not match.
Page 518 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-23. Flow When Setting WUPn = 0 upon Address Match (Including Extension Code Reception) STOP mode state INTIICAn = 1? WUPn = 0 Wait Waits for 5 clocks. Reading IICSn Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
Page 519 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICAn START SPIEn = 1 WUPn = 1 STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICAn.
Page 520 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.14 Communication reservation (1) When communication reservation function is enabled (bit n (IICRSVn) of IICA flag register n (IICFn) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
Page 521 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-25 shows the communication reservation timing. Figure 12-25. Communication Reservation Timing Write to Program processing STTn = 1 IICAn Communi- Set SPDn cation Hardware processing STDn reservation INTIICAn SCLAn SDAAn Generate by master device with bus mastership...
Page 522 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-27. Communication Reservation Protocol SET1 STTn Sets STTn flag (communication reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Note 1 Secures wait time by software.
Page 523 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1) When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 524 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.5.15 Cautions (1) When STCENn = 0 Immediately after I C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 525 This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the RL78/G1P looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave.
Page 526 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 12-28. Master Operation in Single-Master System START Note Initializing I C bus Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 12.3.8 Port mode register 6 (PM6)).
Page 527 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 12-29. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. Setting port (see 12.3.8 Port mode register 6 (PM6)).
Page 528 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-29. Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STTn = 1 (generates a start condition). Note Secure wait time by software. Wait MSTSn = 1? INTIICAn interrupt occurs? Waits for bus release (communication being reserved).
Page 529 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-29. Master Operation in Multi-Master System (3/3) Starts communication Writing IICAn (specifies an address and transfer direction). INTIICAn interrupt occurs? Waits for detection of ACK. MSTSn = 1? ACKDn = 1? TRCn = 1?
Page 530 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
Page 531 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
Page 532 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following operations are performed.
Page 533 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIMn = 0 SPTn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 1000×110B...
Page 534 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIMn = 0 STTn = 1 SPTn = 1 AD6 to AD0 R/W ACK D7 to D0...
Page 535 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIMn = 0 SPTn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 1010×110B 2: IICSn = 1010×000B...
Page 536 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIMn = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0001×110B...
Page 537 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches with SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 0001×110B...
Page 538 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0...
Page 539 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
Page 540 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIMn = 0...
Page 541 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 0010×010B...
Page 542 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 0010×010B...
Page 543 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
Page 544 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 00000001B Remark : Generated only when SPIEn = 1...
Page 545 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0101×110B 2: IICSn = 0001×100B 3: IICSn = 0001××00B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 ×:...
Page 546 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0110×010B 2: IICSn = 0010×110B 3: IICSn = 0010×100B 4: IICSn = 0010××00B 5: IICSn = 00000001B...
Page 547 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0110×010B Sets LRELn = 1 by software 2: IICSn = 00000001B...
Page 548 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 10001110B 2: IICSn = 01000100B 3: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1...
Page 549 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (ii) Extension code AD6 to AD0 R/W ACK D7 to Dm AD6 to AD0 D7 to D0 1: IICSn = 1000×110B 2: IICSn = 01100010B Sets LRELn = 1 by software 3: IICSn = 00000001B...
Page 550 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICSn = 1000×110B...
Page 551 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 AD6 to AD0 R/W ACK D7 to D0 1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Page 552 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIMn = 0 SPTn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICSn = 1000×110B...
Page 553 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA 12.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 554 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICAn <2>...
Page 555 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 12-32 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 556 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4) (2) Address ~ data ~ data Master side Note 1 Note 1 IICAn <5>...
Page 557 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 12-32 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 558 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4) (3) Data ~ data ~ Stop condition Master side Note 1 IICAn <9>...
Page 559 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 12-32 are explained below. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device.
Page 560 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4) (4) Data ~ restart condition ~ address Master side IICAn <iii> ACKDn (ACK detection)
Page 561 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The following describes the operations in Figure 12-32 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the processing to step <iii>, the data transmission step.
Page 562 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICAn <2> ACKDn (ACK detection) WTIMn <5>...
Page 563 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 12-33 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 564 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Address ~ data ~ data Master side IICAn ACKDn (ACK detection) WTIMn <5>...
Page 565 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 12-33 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 566 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA Figure 12-33. Example of Slave to Master Communication (8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition Master side IICAn ACKDn...
Page 567 RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 12-33 are explained below. <8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICAn: end of transfer).
Page 568 RL78/G1P CHAPTER 13 DMA CONTROLLER CHAPTER 13 DMA CONTROLLER The RL78/G1P has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed.
Page 569 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 13-1. Configuration of DMA Controller Item Configuration  DMA SFR address registers 0, 1 (DSA0, DSA1) Address registers  DMA RAM address registers 0, 1 (DRA0, DRA1) ...
Page 570 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.2.2 DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (see Table 13-2) can be set to this register.
Page 571 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.2.3 DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).
Page 572 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers.  DMA mode control register n (DMCn)  DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0, 1) R01UH0895EJ0100 Rev.1.00...
Page 573 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.3.1 DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
Page 574 RL78/G1P CHAPTER 13 DMA CONTROLLER Figure 13-4. Format of DMA Mode Control Register n (DMCn) (2/2) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H Symbol <7> <6> <5> <4> DMCn STGn DRSn DWAITn IFCn2 IFCn1 IFCn0 Note IFCn2 IFCn1 IFCn0...
Page 575 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.3.2 DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
Page 576 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.4 Operation of DMA Controller 13.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.
Page 577 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn). DRSn DMA Transfer Mode Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)
Page 578 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.5 Example of Setting of DMA Controller 13.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below.  Consecutive transmission of CSI00 (256 bytes)  DMA channel 0 is used for DMA transfer.
Page 579 RL78/G1P CHAPTER 13 DMA CONTROLLER Figure 13-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 10H DRA0 = FB00H DBC0 = 0100H DMC0 = 46H Setting for CSI transfer DST0 = 1 DMA is started.
Page 580 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.  Consecutive capturing of A/D conversion results.  DMA channel 1 is used for DMA transfer.
Page 581 RL78/G1P CHAPTER 13 DMA CONTROLLER Figure 13-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs.
Page 582 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below.  Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception.
Page 583 RL78/G1P CHAPTER 13 DMA CONTROLLER Figure 13-9. Example of Setting for UART Consecutive Reception + ACK Transmission Start INTSR0 interrupt routine DEN0 = 1 DSA0 = 12H STG0 = 1 DRA0 = FE00H DBC0 = 0040H DMC0 = 00H DMA0 transfer...
Page 584 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1.
Page 585 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes.
Page 586 RL78/G1P CHAPTER 13 DMA CONTROLLER Figure 13-11. Forced Termination of DMA Transfer (2/2) Example 3  Procedure for forcibly terminating the DMA  Procedure for forcibly terminating the DMA transfer for one channel if both channels are used transfer for both channels if both channels are used...
Page 587 RL78/G1P CHAPTER 13 DMA CONTROLLER 13.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, their priority are DMA channel 0 >...
Page 588 RL78/G1P CHAPTER 13 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.  CALL !addr16  CALL $!addr20  CALL !!addr20  CALL  CALLT [addr5] ...
Page 589 RL78/G1P CHAPTER 14 EVENT LINK CONTROLLER (ELC) CHAPTER 14 EVENT LINK CONTROLLER (ELC) 14.1 Functions of ELC The event link controller (ELC) mutually connects (links) events output from each peripheral function. By linking events, it becomes possible to coordinate operation between peripheral functions directly without going through the CPU.
Page 590 RL78/G1P CHAPTER 14 EVENT LINK CONTROLLER (ELC) 14.3 Registers Controlling ELC Table 14-1 lists the registers controlling ELC. Table 14-1. Registers Controlling ELC Item Configuration Control register Event Output Destination Select Register n (ELSELRn) 14.3.1 Event output destination select register n (ELSELRn) (n = 00 to 09) An ELSELRn register links each event signal to an operation of an event-receiving peripheral function (link destination peripheral function) after reception.
Page 591 RL78/G1P CHAPTER 14 EVENT LINK CONTROLLER (ELC) Table 14-2. Correspondence Between ELSELRn (n = 00 to 09) Registers and Peripheral Functions Register Name Event Generator (Output Origin of Event Input n) Event Description ELSELR00 External interrupt edge detection 0 INTP0...
Page 592 RL78/G1P CHAPTER 14 EVENT LINK CONTROLLER (ELC) 14.4 Operation The path for using an event signal generated by a peripheral function as an interrupt request to the interrupt control circuit is independent from the path for using it as an ELC event. Therefore, each event signal can be used as an event signal for operation of an event-receiving peripheral function, regardless of interrupt control.
Page 593 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS CHAPTER 15 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. 15.1 Interrupt Function Types The following two types of interrupt functions are used.
Page 594 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Table 15-1. Interrupt Source List (1/2) Interrupt Interrupt Source Internal/ Vector Type External Table Name Trigger Address Note 3 Maskable INTWDTI Watchdog timer interval Internal 00004H (75% of overflow time+1/2f Note 4 INTLVI Voltage detection...
Page 595 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Table 15-1. Interrupt Source List (2/2) Interrupt Internal/ Vector Interrupt Source Type External Table Address   Software Execution of BRK instruction 0007EH    Reset RESET RESET pin input 00000H Power-on-reset Note 3...
Page 596 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Interrupt Priority controller address generator request Standby release signal (B) External maskable interrupt (INTPn) Internal bus External interrupt edge...
Page 597 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions.  Interrupt request flag registers (IF0L, IF0H, IF1L)  Interrupt mask flag registers (MK0L, MK0H, MK1L)  Priority specification flag registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L) ...
Page 598 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 599 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. The MK0L, MK0H, and MK1L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the MK0L and MK0H registers are combined to form 16-bit registers MK0, they can be set by a 16-bit memory manipulation instruction.
Page 600 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
Page 601 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0) These registers specify the valid edge for INTP0 to INTP5. The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 602 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.
Page 603 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.4 Interrupt Servicing Operations 15.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 604 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending ××PR No (Low priority) (××PR ≥ (ISP1, ISP0) Interrupt request held pending Higher priority...
Page 605 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction Instruction jump to interrupt servicing program xxIF 9 clocks Remark 1 clock: 1/f : CPU clock) Figure 15-9.
Page 606 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
Page 607 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Table 15-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Software Interrupt Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Request...
Page 608 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz...
Page 609 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00) INTxx...
Page 610 RL78/G1P CHAPTER 15 INTERRUPT FUNCTIONS 15.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 611 RL78/G1P CHAPTER 16 STANDBY FUNCTION CHAPTER 16 STANDBY FUNCTION 16.1 Standby Function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high- speed system clock oscillator or high-speed on-chip oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 612 RL78/G1P CHAPTER 16 STANDBY FUNCTION 16.2 Registers Controlling Standby Function The standby function is controlled by the following two registers.  Oscillation stabilization time counter status register (OSTC)  Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR. For registers which control the SNOOZE mode, CHAPTER 9 A/D CONVERTER and CHAPTER 11 SERIAL ARRAY UNIT.
Page 613 RL78/G1P CHAPTER 16 STANDBY FUNCTION 16.2.1 Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case.
Page 614 RL78/G1P CHAPTER 16 STANDBY FUNCTION 16.2.2 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using the OSTS register after the STOP mode is released.
Page 615 RL78/G1P CHAPTER 16 STANDBY FUNCTION 16.3 Standby Function Operation 16.3.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock or high-speed on-chip oscillator clock.
Page 616 RL78/G1P CHAPTER 16 STANDBY FUNCTION Table 16-1. Operating Statuses in HALT Mode HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on...
Page 617 RL78/G1P CHAPTER 16 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 618 RL78/G1P CHAPTER 16 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Page 619 RL78/G1P CHAPTER 16 STANDBY FUNCTION 16.3.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the high-speed on-chip oscillator clock, X1 clock, or external main system clock.
Page 620 RL78/G1P CHAPTER 16 STANDBY FUNCTION Table 16-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on...
Page 621 RL78/G1P CHAPTER 16 STANDBY FUNCTION speed on-chip oscillator clock before the execution of the STOP instruction. Before changing the CPU clock from the high-speed on-chip oscillator clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC).
Page 622 RL78/G1P CHAPTER 16 STANDBY FUNCTION Remarks 1. The clock supply stop time varies depending on the temperature conditions and STOP mode period. 2. The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged.
Page 623 RL78/G1P CHAPTER 16 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Page 624 RL78/G1P CHAPTER 16 STANDBY FUNCTION 16.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSIp, UARTq, or the A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock.
Page 625 RL78/G1P CHAPTER 16 STANDBY FUNCTION Table 16-3. Operating Statuses in SNOOZE Mode SNOOZE Mode Setting When Inputting CSIp/UARTq Data Reception Signal or A/D Converter Timer Trigger Signal While in STOP Mode Item When CPU Is Operating on High-speed On-chip Oscillator Clock (f...
Page 626 RL78/G1P CHAPTER 16 STANDBY FUNCTION (2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode Figure 16-7. When the Interrupt Request Signal is Generated in the SNOOZE Mode STOP Trigger instruction detection Interrupt request Standby release...
Page 627 RL78/G1P CHAPTER 17 RESET FUNCTION CHAPTER 17 RESET FUNCTION The following seven operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit...
Page 628 RL78/G1P CHAPTER 17 RESET FUNCTION R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 629 RL78/G1P CHAPTER 17 RESET FUNCTION 17.1 Timing of Reset Operation ___________ This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on ___________ the RESET pin.
Page 630 RL78/G1P CHAPTER 17 RESET FUNCTION Notes 1. Reset times (times for release from the external reset state) After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use. 0.399 ms (typ.), 0.519 ms (max.) when the LVD is off.
Page 631 RL78/G1P CHAPTER 17 RESET FUNCTION Table 17-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (the X1 and X2 pins are input port mode)
Page 632 RL78/G1P CHAPTER 17 RESET FUNCTION Table 17-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (00000H, 00001H) are set. Stack pointer (SP) Undefined Program status word (PSW)
Page 633 RL78/G1P CHAPTER 17 RESET FUNCTION Table 17-2. Hardware Statuses After Reset Acknowledgment (2/3) Status After Reset Hardware Note 1 Acknowledgment Clock output/buzzer Clock output select registers 0, 1 (CKS0, CKS1) output controller Note 2 1AH/9AH Watchdog timer Enable register (WDTE)
Page 634 RL78/G1P CHAPTER 17 RESET FUNCTION Table 17-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Note 1 Acknowledgment Note 2 Reset function Reset control flag register (RESF) Undefined Note 2 Voltage detector (LVD) Voltage detection register (LVIM) Notes 2, 3...
Page 635 17.2 Register for Confirming Reset Source 17.2.1 Reset control flag register (RESF) Many internal reset generation sources exist in the RL78/G1P. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction.
Page 636 RL78/G1P CHAPTER 17 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 17-3. Table 17-3. RESF Register Status When Reset Request Is Generated Reset Source RESET Input Reset by Reset by...
Page 637 RL78/G1P CHAPTER 17 RESET FUNCTION Figure 17-5. Procedure for Checking Reset Source After reset acceptance Read the RESF register (clear the RESF register) and Read RESF register store the value of the RESF register in any RAM. TRAP of RESF...
Page 638 RL78/G1P CHAPTER 18 POWER-ON-RESET CIRCUIT CHAPTER 18 POWER-ON-RESET CIRCUIT 18.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions.  Generates internal reset signal at power on. The reset is released when the supply voltage (V ) exceeds the detection voltage (V ).
Page 639 RL78/G1P CHAPTER 18 POWER-ON-RESET CIRCUIT 18.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 18-1. Figure 18-1. Block Diagram of Power-on-reset Circuit Internal reset signal − Reference voltage source 18.3 Operation of Power-on-reset Circuit The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below.
Page 640 RL78/G1P CHAPTER 18 POWER-ON-RESET CIRCUIT Figure 18-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/3) ____________ (1) When the externally input reset signal on the RESET pin is used Supply voltage (V Note 5...
Page 641 RL78/G1P CHAPTER 18 POWER-ON-RESET CIRCUIT Figure 18-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (2) LVD interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (V Note 3...
Page 642 RL78/G1P CHAPTER 18 POWER-ON-RESET CIRCUIT Figure 18-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3) (3) When LVD is reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1) Supply voltage (V Lower limit voltage for guaranteed operation = 1.50 V (TYP.)
Page 643 RL78/G1P CHAPTER 18 POWER-ON-RESET CIRCUIT 18.4 Cautions for Power-on-reset Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POR detection voltage ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 644 RL78/G1P CHAPTER 18 POWER-ON-RESET CIRCUIT Figure 18-3. Example of Software Processing After Reset Release (2/2)  Checking reset source Check reset source TRAP of RESF register = 1? Reset processing by Note illegal instruction execution WDTRF of RESF register = 1?
Page 645 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR CHAPTER 19 VOLTAGE DETECTOR 19.1 Functions of Voltage Detector The voltage detector (LVD) has the following functions.  The LVD circuit compares the supply voltage (V ) with the detection voltage (V ), and generates an...
Page 646 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR 19.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 19-1. Figure 19-1. Block Diagram of Voltage Detector N-ch Internal reset signal LVDH − LVDL INTLVI Option byte (000C1H)
Page 647 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR 19.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 648 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR 19.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation input sets this register to 00H/01H/81H Figure 19-3.
Page 649 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR Table 19-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0  LVD setting (interrupt & reset mode) Detection voltage Option byte setting value...
Page 650 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR 19.4 Operation of Voltage Detector 19.4.1 When used as reset mode  When starting operation Start in the following initial setting state. Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V ) by using the option byte 000C1H.
Page 651 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR Figure 19-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.) Time Cleared...
Page 652 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR 19.4.2 When used as interrupt mode  When starting operation Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (V ) by using the option byte 000C1H. Start in the following initial setting state.
Page 653 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR Figure 19-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Note 2 Note 2 Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.)
Page 654 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR 19.4.3 When used as interrupt and reset mode  When starting operation Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (V LVDH ) by using the option byte 000C1H.
Page 655 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR Figure 19-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask, determine that a condition of V...
Page 656 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 19-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode.
Page 657 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR Figure 19-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of V is V < V after releasing the mask, LVDH a reset is generated because of LVIMD = 1 (reset mode).
Page 658 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 19-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode.
Page 659 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400  s or 5 clocks of f is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0) clear the LVIMD bit for initialization.
Page 660 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR 19.5 Cautions for Voltage Detector (1) Voltage fluctuation when power is supplied In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVD detection voltage, the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 661 RL78/G1P CHAPTER 19 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (V ) < LVD detection voltage (V ) until the time LVD reset has been generated.
Page 662 This detects data errors in the flash memory by performing CRC operations. Two CRC functions are provided in the RL78/G1P that can be used according to the application or purpose of use.  High-speed CRC: The CPU can be stopped and a high-speed check executed on its entire code flash memory area during the initialization routine.
Page 663 The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The high-speed CRC provided in the RL78/G1P can be used to check the entire code flash memory area during the initialization routine. The high-speed CRC can be executed only when the program is allocated on the RAM and in the HALT mode of the main system clock.
Page 664 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.3.1 Flash memory CRC control register (CRC0CTL) This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range. The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 665 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.3.3 Operation flow Figure 20-3 shows the flowchart of flash memory CRC operation function (high-speed CRC). Figure 20-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ;...
Page 666 CPU is operating. In the RL78/G1P, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked can be specified by using software (a user-created program).
Page 667 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.4.2 CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (f ) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register.
Page 668 The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RAM of the RL78/G1P. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read.
Page 669 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS Figure 20-8. RAM Parity Error Check Flow Check start Note RPERF = 1 Disable parity error resets RPERDIS = 1 RAM check Read RAM RAM check Parity error has occurred RPEF = 1 Confirm that a parity error has occurred.
Page 670 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.6 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space.
Page 671 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.7 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function.
Page 672 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.8 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed.
Page 673 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.8.1 Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function. The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Page 674 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.9 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (f ) and measuring the pulse width of the input signal to channel 1 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined.
Page 675 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.9.1 Timer input select register 0 (TIS0) The TIS0 register is used to select the timer input of channels 0 and 1 of the timer array unit 0 (TAU0). By selecting the internal low-speed oscillation clock for the timer input, its pulse width can be measured to determine whether the proportional relationship between the internal low-speed oscillation clock and the timer operation clock is correct.
Page 676 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.10 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function is used to check whether the A/D converter is operating normally by executing A/D conversions of the positive reference voltage and negative reference voltage of the A/D converter, analog input channel (ANI), temperature sensor output voltage, and internal reference voltage.
Page 677 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS Figure 20-15. Configuration of A/D Test Function • ADISS • ADS4 to ADS0 ANI0/AV REFP ANI1/AV REFM ANIxx • ADTES1, ADTES0 ANIxx Note Temperature sensor Internal reference Note voltage (1.45 V) A/D convertor + side reference voltage •...
Page 678 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.10.1 A/D test register (ADTES) This register is used to select the A/D converter’s positive reference voltage, the A/D converter’s negative reference voltage, or the analog input channel (ANIxx), temperature sensor output voltage, or internal reference voltage (1.45 V) as the target of A/D conversion.
Page 679 RL78/G1P CHAPTER 20 SAFETY FUNCTIONS 20.10.2 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. Set A/D test register (ADTES) to 00H when measuring the ANIxx/temperature sensor output /internal reference voltage (1.45 V).
Page 680 CHAPTER 21 REGULATOR CHAPTER 21 REGULATOR 21.1 Regulator Overview The RL78/G1P contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the  regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1...
Page 681 CHAPTER 22 OPTION BYTE 22.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the RL78/G1P form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Page 682 RL78/G1P CHAPTER 22 OPTION BYTE 22.2 Format of User Option Byte Figure 22-1. Format of User Option Byte (000C0H) Address: 000C0H WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTINIT Use of interval interrupt of watchdog timer Interval interrupt is not used.
Page 683 RL78/G1P CHAPTER 22 OPTION BYTE Figure 22-2. Format of User Option Byte (000C1H) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0  LVD setting (interrupt & reset mode) Detection voltage Option byte setting value Mode setting VPOC2 VPOC1 VPOC0...
Page 684 RL78/G1P CHAPTER 22 OPTION BYTE Figure 22-3. Format of User Option Byte (000C2H) Address: 000C2H CMODE1 CMODE0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating Operating frequency range voltage range LS (low-speed main) mode 1 to 8 MHz 2.7 to 3.6 V...
Page 685 RL78/G1P CHAPTER 22 OPTION BYTE 22.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 22-4. Format of On-chip Debug Option Byte (000C3H) Address: 000C3H OCDENSET OCDERSD OCDENSET OCDERSD Control of on-chip debug operation Disables on-chip debug operation.
Page 686 RL78/G1P CHAPTER 22 OPTION BYTE 22.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the assembler linker option, in addition to describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions exist in the source, as mentioned below.
Page 687 CHAPTER 23 FLASH MEMORY The RL78/G1P incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data.
Page 688 Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the RL78/G1P has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system.
Page 689 RL78/G1P CHAPTER 23 FLASH MEMORY Table 23-1. Wiring Between RL78/G1P and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Pin Name Pin No. 24-pin 32-pin Signal Name Pin Function HWQFN (4 × 4) LQFP (7 × 7)
Page 690 RL78/G1P CHAPTER 23 FLASH MEMORY 23.1.1 Programming environment The environment required for writing a program to the flash memory of the RL78/G1P is illustrated below. Figure 23-1. Environment for Writing Program to Flash Memory PG-FP6 E1, E2, E2 Lite, E20...
Page 691 UART (TOOLTxD, TOOLRxD) RL78/G1P (such as microcontroller and ASIC) TOOL0 Processing to write data to or delete data from the RL78/G1P by using an external device is performed on-board. Off- board writing is not possible. R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 692 CHAPTER 23 FLASH MEMORY 23.2.2 Communication mode Communication between the external device and the RL78/G1P is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78/G1P. Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps Figure 23-4.
Page 693 (see 27.9 Timing of Entry to Flash Memory Programming Modes). 2. The SAU and IICA pins are not used for communication between the RL78/G1P, and dedicated flash memory programmer, because single-line UART (TOOL0 pin) is used.
Page 694 RL78/G1P CHAPTER 23 FLASH MEMORY 23.3.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status...
Page 695 CHAPTER 23 FLASH MEMORY 23.4 Data Flash 23.4.1 Data flash overview In addition to 16 KB of code flash memory, the RL78/G1P with data flash includes 2 KB of data flash memory for storing data. F F F F F H...
Page 696 RL78/G1P CHAPTER 23 FLASH MEMORY An overview of the data flash memory is provided below. For details of a method for rewriting the data flash memory, refer to the RL78 Family Data Flash Library User’s Manual.  The data flash memory can be written to by using the flash memory programmer or an external device ...
Page 697 RL78/G1P CHAPTER 23 FLASH MEMORY 23.4.3 Procedure for accessing data flash memory The data flash memory is stopped after a reset ends. To access the data flash, make initial settings according to the following procedure. <1> Set bit 0 (DFLEN) of the data flash control register (DFLCTL) to 1.
Page 698 RL78/G1P CHAPTER 23 FLASH MEMORY 23.5 Programming Method 23.5.1 Controlling flash memory The following figure illustrates a flow for rewriting the code flash memory through serial programming. Figure 23-7. Flash Memory Manipulation Procedure Start Flash memory programming Controlling TOOL0 pin and RESET pin...
Page 699 CHAPTER 23 FLASH MEMORY 23.5.2 Flash memory programming mode To rewrite the contents of the flash memory, set the RL78/G1P in the flash memory programming mode. To enter the mode, set as follows. <When programming by using the dedicated flash memory programmer>...
Page 700 RL78/G1P CHAPTER 23 FLASH MEMORY Table 23-4. Relationship Between TOOL0 Pin and Operation Mode After Reset Release TOOL0 Operation Mode Normal operation mode Flash memory programming mode There are two flash memory programming modes: wide voltage mode and full speed mode. The supply voltage value applied to the microcontroller during write operations and the setting information of the user option byte for setting of the flash memory programming mode determine which mode is selected.
Page 701 The RL78/G1P communicates with the dedicated flash memory programmer or external device by using commands. The signals sent from the flash memory programmer or external device to the RL78/G1P are called commands, and the signals sent from the RL78/G1P to the dedicated flash memory programmer or external device are called response.
Page 702 RL78/G1P CHAPTER 23 FLASH MEMORY Table 23-8. Response Names Response Name Function Acknowledges command/data. Acknowledges illegal command/data. R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 703 CHAPTER 23 FLASH MEMORY 23.5.5 Description of signature data When the “silicon signature” command is performed, the RL78/G1P information (such as the part number, flash memory configuration, and programming firmware version) can be obtained. Tables 23-9 and 23-10 show signature data list and example of signature data list.
Page 704 CHAPTER 23 FLASH MEMORY 23.6 Security Settings The RL78/G1P supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command.
Page 705 RL78/G1P CHAPTER 23 FLASH MEMORY Table 23-11. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Block Erase Write Prohibition of block erase Blocks cannot be erased. Can be performed. Note Prohibition of writing Blocks can be erased.
Page 706 23.7 Flash Memory Programming by Self-programming The RL78/G1P supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the RL78/G1P self-programming library, it can be used to upgrade the program in the field.
Page 707 RL78/G1P CHAPTER 23 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self-programming library. Figure 23-10. Flow of Self-programming (Rewriting Flash Memory) Flash memory control start Initialize flash environment Flash shield window setting...
Page 708 Figure 23-11. Flash Shield Window Setting Example (Target Devices: RL78/G1P, Start Block: 04H, End Block: 06H) 03FFFH Methods by which writing can be performed...
Page 709 RL78/G1P CHAPTER 23 FLASH MEMORY 23.8 Processing Time for Each Command When PG-FP6 Is in Use (Reference Value) The following shows the processing time for each command (reference value) when PG-FP6 is used as a dedicated flash memory programmer. Table 23-15. Processing Time for Each Command When PG-FP6 Is in Use (Reference Value)
Page 710 Lite, E20 on-chip debugging emulator. Serial communication is performed by using a single-line UART that uses the TOOL0 pin. Caution The RL78/G1P has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Page 711 24.2 On-chip Debug Security ID The RL78/G1P has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 22 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content.
Page 712 RL78/G1P CHAPTER 24 ON-CHIP DEBUG FUNCTION Figure 24-2. Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area Note 1 (512 bytes or Note 2 256 bytes Stack area for debugging Internal RAM...
Page 713 RL78/G1P CHAPTER 25 BCD CORRECTION CIRCUIT CHAPTER 25 BCD CORRECTION CIRCUIT 25.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/subtracting the BCD correction result register (BCDADJ).
Page 714 RL78/G1P CHAPTER 25 BCD CORRECTION CIRCUIT 25.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
Page 715 RL78/G1P CHAPTER 25 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.
Page 716 RL78/G1P CHAPTER 26 INSTRUCTION SET CHAPTER 26 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Family User’s Manual: Software. R01UH0895EJ0100 Rev.1.00...
Page 717 RL78/G1P CHAPTER 26 INSTRUCTION SET 26.1 Conventions Used in Operation List 26.1.1 Operand identifiers and specification methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them.
Page 718 RL78/G1P CHAPTER 26 INSTRUCTION SET 26.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 26-2. Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator X register...
Page 719 RL78/G1P CHAPTER 26 INSTRUCTION SET 26.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 26-3. Symbols in “Flag” Column Symbol Change of Flag Value...
Page 720 RL78/G1P CHAPTER 26 INSTRUCTION SET 26.2 Operation List Table 26-5. Operation List (1/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  r  byte 8-bit data r, #byte transfer × × × ...
Page 721 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (2/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  A  sfr 8-bit data A, sfr transfer  sfr  A sfr, A A  (DE) A, [DE] ...
Page 722 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (3/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY A  (HL + B) 8-bit data A, [HL+B] transfer  (HL + B)  A [HL+B], A A ...
Page 723 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (4/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  A  (HL+B) 8-bit data A, [HL+B] transfer  A  ((ES, HL)+B) A, ES:[HL+B] ...
Page 724 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (5/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY AX  (DE) 16-bit MOVW AX, [DE] data  (DE)  AX [DE], AX transfer AX  (ES, DE) AX, ES:[DE] ...
Page 725 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (6/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY BC  (addr16) 16-bit MOVW BC, !addr16 data BC  (ES, addr16) BC, ES:!addr16 transfer DE  (addr16) DE, !addr16 DE ...
Page 726 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (7/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  A, CY  A+byte+CY 8-bit ADDC A, #byte × × × operation  (saddr), CY  (saddr) +byte+CY saddr, #byte ×...
Page 727 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (8/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  A, CY  A – byte – CY 8-bit SUBC A, #byte × × ×...
Page 728 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (9/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  A  Abyte 8-bit A, #byte × operation  (saddr)  (saddr)byte saddr, #byte ×...
Page 729 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (10/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  8-bit A, #byte A – byte × × × operation !addr16, #byte (addr16) – byte ×...
Page 730 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (11/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  AX, CY  AX+word 16-bit ADDW AX, #word × × × operation  AX, CY  AX+AX AX, AX ×...
Page 731 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (12/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY  AX  A  X Multiply, MULU Divide, Multiply & accumu- late Notes 1.
Page 732 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (13/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  r  r+1 Increment/ × × decrement  (addr16)  (addr16)+1 !addr16 × × ...
Page 733 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (14/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY   A  A Rotate A, 1 (CY, A )×1 ×   A  A...
Page 734 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (15/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  CY  CY  A.bit XOR1 CY, A.bit × manipulate  CY  CY  PSW.bit CY, PSW.bit...
Page 735 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (16/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  (SP – 2)  (PC+2) , (SP – 3)  (PC+2) CALL Call/ (SP – 4)  (PC+2) , PC ...
Page 736 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (17/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  (SP  1)  PSW, (SP  2)  00H, Stack PUSH manipulate SP  SP2 ...
Page 737 RL78/G1P CHAPTER 26 INSTRUCTION SET Table 26-5. Operation List (18/18) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY  PC  PC + 4 + jdisp8 if (saddr).bit = 0 Note 3 Condition saddr.bit, $addr20 al branch ...
Page 738 Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 739 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25C) (1/2) Parameter Symbols Conditions Ratings Unit 0.5 to +4.6 Supply voltage 0.5 to +0.3 0.3 to +2.8 REGC pin input voltage REGC IREGC and 0.3 to V Note 1 +0.3...
Page 740 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25C) (2/2) Parameter Symbols Conditions Ratings Unit 40 Output current, high Per pin P10 to P17, P30 to P35, P40 40 Total of all pins 140 mA 100 P10 to P17, P30, P35 0.5...
Page 741 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.2 Oscillator Characteristics 27.2.1 X1 oscillator characteristics = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit 2.7 V  V  3.6 V...
Page 742 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.3 DC Characteristics 27.3.1 Pin characteristics = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) (1/3) Items Symbol Conditions MIN. TYP. MAX. Unit 2.0 Output current, high Note 1...
Page 743 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) (2/3) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 Per pin for P10 to P17, P30 to P35, P40...
Page 744 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) (3/3) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high P10 to P17, P30 to P35, P40, P121, P122, P137, 0.8V...
Page 745 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.3.2 Supply current characteristics = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) (1/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply Note 1 Operating HS (high- Note 3...
Page 746 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) (2/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit HS (high-speed Supply Note 2 HALT = 32 MHz Note 4 = 3.0 V 0.60...
Page 747 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) (3/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit  Notes 1, 2, 3 Watchdog timer = 15 kHz 0.22 operating current...
Page 748 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.4 AC Characteristics = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit  Instruction cycle (minimum Main system clock HS (high-speed main) mode 0.03125...
Page 749 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS Minimum Instruction Execution Time during Main System Clock Operation TCY vs V (HS (high-speed main) mode) When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.05 0.03125 0.01 Supply voltage V R01UH0895EJ0100 Rev.1.00...
Page 750 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS TCY vs V (LS (low-speed main) mode) When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.125 0.01 Supply voltage V AC Timing Test Points Test points External System Clock Timing EXCLK R01UH0895EJ0100 Rev.1.00...
Page 751 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS TI/TO Timing TI00 to T03 TO00 to TO03 Interrupt Request Input Timing INTL INTH INTP0 to INTP5 RESET Input Timing RESET R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 752 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.5 Peripheral Functions Characteristics AC Timing Test Points Test points 27.5.1 Serial array unit (1) During communication at same potential (UART mode) = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V)
Page 753 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) = -40 to +85C, 2.7 V ≤ V ≤ 3.6 V, V = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN.
Page 754 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) Parameter Symbol Conditions HS (high-speed main)
Page 755 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at same potential) SCKp RL78 User's device microcontroller CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
Page 756 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.5.2 Serial interface IICA = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) Parameter Symbol Conditions Standard Fast Mode Fast Mode Unit Mode Plus MIN. MAX. MIN. MAX. MIN. MAX.
Page 757 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.5.3 Dedicated Flash Memory Programmer Communication (UART) = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 115.2 k 27.6 Analog Characteristics 27.6.1 A/D converter characteristics...
Page 758 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS (2) When AV (ADREFP1 = 0, ADREFP0 = 0), AV (ADREFM = 0), target ANI pin: ANI0 to ANI7 REF (+) REF () = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V, Reference voltage (+) = V , Reference voltage () = V...
Page 759 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS (4) When AV (ADREFP1 = 0, ADREFP0 = 0), AV (ADREFM = 0), target ANI pin: ANI16, REF (+) REF () internal reference voltage, and temperature sensor output voltage = 40 to +85C, 2.7 V  V ...
Page 760 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.6.2 Temperature sensor/internal reference voltage characteristics = 40 to +85C, 2.7 V  V  3.6 V, V = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit = +25  C...
Page 761 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.6.4 POR circuit characteristics = 40 to +85C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Power supply rise time 1.47 1.51 1.55 Power supply fall time 1.46 1.50 1.54 ...
Page 762 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.6.5 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode = 40 to +85C, V  V  3.6 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Power supply rise time 3.07...
Page 763 The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation.
Page 764 RL78/G1P CHAPTER 27 ELECTRICAL SPECIFICATIONS 27.9 Timing of Entry to Flash Memory Programming Modes Parameter Symbol Conditions MIN. TYP. MAX. Unit How long from when an external POR and LVD reset must end before the SUINIT reset ends until the initial external reset ends.
Page 765 RL78/G1P CHAPTER 28 PACKAGE DRAWINGS CHAPTER 28 PACKAGE DRAWINGS 28.1 24-pin Products R5F11Z7AANA, R5F11Z7ADNA JEITA Package code MASS(TYP.)[g] RENESAS code P-HWQFN024-4x4-0.50 PWQN0024KF-A 0.04 aaa C INDEX AREA (D/2 X E/2) aaa C ccc C SEATING PLANE (A3) A1 b(24X) C A B...
Page 766 RL78/G1P CHAPTER 28 PACKAGE DRAWINGS 28.2 32-pin Products R5F11ZBAAFP, R5F11ZBADFP R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 767 RL78/G1P APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition Edition Description Chapter Rev.1.00 First edition issued Throughout R01UH0895EJ0100 Rev.1.00 Nov 29, 2019...
Page 768 RL78/G1P User’s Manual: Hardware Publication Date: Rev.1.00 Nov 29, 2019 Published by: Renesas Electronics Corporation...
Page 769 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Tel: +1-408-432-8888, Fax: +1-408-434-5351 Renesas Electronics Canada Limited...
Page 770 RL78/G1P R01UH0895EJ0100...

Renesas RL78/G1P Hardware User Manual

Chapter 1 Outline

Features

List of Part Numbers

Pin Configuration (Top View)

Pin Identification

Block Diagram

Outline of Functions

Chapter 2 Pin Functions

Pin Function List

Functions Other than Port Pins

Description of Pin Functions

Connection of Unused Pins

Chapter 3 Cpu Architecture

Memory Space

Processor Registers

Instruction Address Addressing

Addressing for Processing Data Addresses

Chapter 4 Port Functions

Port Configuration

Registers Controlling Port Function

Port Function Operations

Settings of Port Related Register When Using Alternate Function

Cautions When Using Port Function

Chapter 5 Clock Generator

Functions of Clock Generator

Configuration of Clock Generator

Registers Controlling Clock Generator

System Clock Oscillator

Clock Generator Operation

Controlling Clock

Resonator and Oscillator Constants

Chapter 6 Timer Array Unit

Functions of Timer Array Unit

Configuration of Timer Array Unit

Registers Controlling Timer Array Unit

Basic Rules of Timer Array Unit

Operation of Counter

Channel Output (Tomn Pin) Control

Timer Input (Timn) Control

Independent Channel Operation Function of Timer Array Unit

Simultaneous Channel Operation Function of Timer Array Unit

Cautions When Using Timer Array Unit

Chapter 7 Clock Output/Buzzer Output Controller

Functions of Clock Output/Buzzer Output Controller

Configuration of Clock Output/Buzzer Output Controller

Registers Controlling Clock Output/Buzzer Output Controller

Operations of Clock Output/Buzzer Output Controller

Cautions of Clock Output/Buzzer Output Controller

Chapter 8 Watchdog Timer

Functions of Watchdog Timer

Configuration of Watchdog Timer

Register Controlling Watchdog Timer

Operation of Watchdog Timer

Chapter 9 A/D Converter

Function of A/D Converter

Configuration of A/D Converter

Registers Controlling A/D Converter

A/D Converter Conversion Operations

Input Voltage and Conversion Results

A/D Converter Operation Modes

A/D Converter Setup Flowchart

SNOOZE Mode Function

How to Read A/D Converter Characteristics Table

Cautions for A/D Converter

Chapter 10 D/A Converter

Function of D/A Converter

Configuration of D/A Converter

Configuration of A/D Converter

Operations of D/A Converter

Cautions for D/A Converter

Chapter 11 Serial Array Unit

Functions of Serial Array Unit

Configuration of Serial Array Unit

Registers Controlling Serial Array Unit

Operation Stop Mode

Operation of 3-Wire Serial I/O (CSI00) Communication

Clock Synchronous Serial Communication with Slave Select Input Function

Quick Links

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