Renesas RL78/G1P Hardware User Manual page 247

RL78/G1P
Figure 7-1. Block Diagram of Clock Output/Buzzer Output Controller
PCLOE1 0 0
f
Prescaler
MAIN
5 3
PCLOE0 0 0
Note For output frequencies available from PCLBUZ0 and PCLBUZ1, see 27.4 AC Characteristics.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Internal bus
Clock output select register 1 (CKS1)
0 0 CCS12 CCS11 CCS10
11 13
f /2 to f /2
MAIN MAIN
4
f to f /2
MAIN MAIN
11 13
f /2 to f /2
MAIN MAIN
4
f to f /2
MAIN MAIN
0 0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
PCLOE1
Clock/buzzer
controller
Output latch
PM15
(P15)
Clock/buzzer
controller
PCLOE0
Output latch
PM12
(P12)
Note
PCLBUZ1 /P15
Note
PCLBUZ0 /TI03/TO03/INTP4/P12
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