Renesas RL78/G1P Hardware User Manual page 311

RL78/G1P
Normal
operation
STOP
mode
SNOOZE
The clock request signal
mode
(an internal signal) is
automatically set to the low
level in the SNOOZE mode.
Normal
operation
If the A/D conversion end interrupt request signal (INTAD) is not generated by setting ADRCK bit and
Notes 1.
ADUL/ADLL register, the result is not stored in the ADCR and ADCRH registers.
The system enters the STOP mode again. If a hardware trigger is input later, A/D conversion operation is
again performed in the SNOOZE mode..
If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or
2.
normal operation mode. Be sure to clear the AWC bit to 0.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 9-37. Flowchart for Setting up SNOOZE Mode
Start of setup
PER0 register setting
ADPC and PMCx
register settings
PMx register setting
•ADM0 register setting
•ADM1 register setting
•ADM2 register setting
•ADUL/ADLL register setting
•ADS register setting
(The order of the settings is
irrelevant.)
Reference voltage
stabilization wait time A
AWC = 1
ADCE bit setting
Enter the STOP mode
generation
Hardware trigger
The A/D conversion operations are performed.
End of A/D conversion
No
INTAD
generation?
Yes
Storage of conversion results
in the ADCR and ADCRH
registers
AWC = 0
Normal operation
CHAPTER 9 A/D CONVERTER
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to analog input.
ANI0 to ANI7 pins: Set using the ADPC register
ANI16 to ANI19 pins: Set using the PMCx register
The ports are set to the input mode.
•ADM0 register
FR2 to FR0, LV1, LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
•ADM1 register
ADTMD1, ADTMD0 bits: These are used to specify the hardware trigger wait mode.
ADSCM bit: One-shot conversion mode
ADTRS1, ADTRS0 bits: These are used to select the hardware trigger signal.
•ADM2 register
ADREFP1, ADREFP0, ADREFM bits: These are used to select the reference voltage.
ADCRK bit: This is used to select the range for the A/D conversion result comparison
value generated by the interrupt signal from AREA1, AREA3, and AREA2.
ADTYP bit: 8-bit/12-bit resolution
•ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
•ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
The reference voltage stabilization wait time count A indicated by A below may be required if the values
of the ADREFP1 and ADREFP0 bits are changed.
If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs
A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1,
respectively.
Immediately before entering the STOP mode, enable the SNOOZE mode by setting the
AWC bit of the ADM2 register to 1.
The AWC bit of the ADM2 register is set (1), and the system enters the A/D conversion
standby status.
After hardware trigger is generated, the system automatically counts up to the
stabilization wait time for A/D power supply and A/D conversion is started in the
SNOOZE mode.
The A/D conversion end interrupt (INTAD) is generated.
The conversion results are stored in the ADCR and ADCRH registers.
Release the SNOOZE mode by clearing the AWC bit of the ADM2 register to 0.
Note 1
Note 2
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