Configuration Of Clock Output/Buzzer Output Controller; Registers Controlling Clock Output/Buzzer Output Controller; Clock Output Select Registers N (Cksn) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

7.2 Configuration of Clock Output/Buzzer Output Controller

The clock output/buzzer output controller includes the following hardware.
Control registers

7.3 Registers Controlling Clock Output/Buzzer Output Controller

7.3.1 Clock output select registers n (CKSn)

These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZn), and set
the output clock.
Select the clock to be output from the PCLBUZn pin by using the CKSn register.
The CKSn register are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Table 7-1. Configuration of Clock Output/Buzzer Output Controller
Item
Clock output select registers n (CKSn)
Port mode register 1 (PM1)
Port register 1 (P1)
Configuration
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