Timer Status Register Mn (Tsrmn) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.3.4 Timer status register mn (TSRmn)

The TSRmn register indicates the overflow status of the counter of channel n.
The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode
(MDmn3 to MDmn1 = 110B). See Table 6-4 for the operation of the OVF bit in each operation mode and set/clear
conditions.
The TSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL.
Reset signal generation clears this register to 0000H.
Address: F01A0H, F01A1H (TSR00) to F01A6H, F01A7H (TSR03)
Symbol 15 14
TSRmn 0 0
OVF
0 Overflow does not occur.
1 Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)
Table 6-4. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer Operation Mode
 Capture mode
 Capture & one-count mode
 Interval timer mode
 Event counter mode
 One-count mode
The OVF bit does not change immediately after the counter has overflowed, but changes upon the
Remark
subsequent capture.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 6-12. Format of Timer Status Register mn (TSRmn)
13 12 11 10
0 0 0 0
Counter overflow status of channel n
OVF Bit
clear
set
clear
set
After reset: 0000H
9 8 7 6
0 0 0 0
Set/Clear Conditions
When no overflow has occurred upon capturing
When an overflow has occurred upon capturing
(Use prohibited)
CHAPTER 6 TIMER ARRAY UNIT
R
5 4 3 2
0 0 0 0

1 0
0 OVF
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