Renesas RL78/G1P Hardware User Manual page 627

RL78/G1P
The following seven operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit
(4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage
(5) Internal reset by execution of illegal instruction
(6) Internal reset by RAM parity error
(7) Internal reset by illegal-memory access
External and internal resets start program execution from the address stored at 00000H and 00001H when the reset
signal is generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD
circuit voltage detection, execution of illegal instruction
hardware is set to the status shown in Table 17-1.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset
processing. A reset by the watchdog timer overflow, execution of illegal instruction, detection of RAM parity error, or
detection of illegal memory access is automatically released, and program execution starts using the high-speed onchip
oscillator clock (see Figures 17-2 and 17-3) after reset processing. Reset by POR and LVD circuit supply voltage
detection is automatically released when V
high-speed on-chip oscillator clock (see CHAPTER 18 POWER-ON-RESET CIRCUIT and CHAPTER 19 VOLTAGE
DETECTOR) after reset processing.
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Cautions 1. For an external reset, input a low level for 10
(To perform an external reset upon power application, a low level of at least 10
continued during the period in which the supply voltage is within the operating range.)
The operating voltage range depends on the setting of the user option byte (000C2H).
The following shows the operating voltage range.
HS (high-speed main) mode: V
LS (low-speed main) mode: V
2. During reset input, the X1 clock, high-speed on-chip oscillator clock, and low-speed on-chip
oscillator clock stop oscillating. External main system clock input becomes invalid.
3. Each of the SFRs and 2nd SFRs are initialized when a reset is applied, so P40 becomes high-
impedance (in the case of an external reset or POR reset) or is pulled-up (in the case of other
types of reset), and the other port pins become high-impedance.
Remark V : POR power supply rise detection voltage
POR
V : LVD detection voltage
LVD
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 17 RESET FUNCTION
Note
Note
, RAM parity error or illegal-memory access, and each item of
 V  V
or V
DD POR DD LVD

= 2.7 to 3.6 V@1 MHz to 24 MHz
DD
= 2.7 to 3.6 V@1 MHz to 8 MHz
DD
CHAPTER 17 RESET FUNCTION
after the reset, and program execution starts using the
s or more to the RESET pin.

s must be
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