Renesas RL78/G1P Hardware User Manual page 532

RL78/G1P
An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is
performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following
operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address does
not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns
from the interrupt (the ready flag is cleared).
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I
remaining in the wait state.
Remark <1> to <3> above correspond to <1> to <3> in Figure 12-31 Slave Operation Flowchart (2).
INTIICAn generated
SPDn = 1?
STDn = 1?
Set ready flag
Interrupt servicing completed
2
12.5.17 Timing of I C interrupt request (INTIICAn) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn, and the value of the
IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Remarks 1. ST:
AD6 to AD0:
R/W:
ACK:
D7 to D0:
SP:
2. n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-31. Slave Operation Flowchart (2)
<1>
Yes
No
<2>
Yes
No
<3>
Communication direction flag
Set communication mode flag
Start condition
Address
Transfer direction specification
Acknowledge
Data
Stop condition
CHAPTER 12 SERIAL INTERFACE IICA
COIn = 1?
Yes
 TRCn
Clear ready flag
No
Clear communication direction
flag, ready flag, and
communication mode flag
2
C bus
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